One nice thing about being a prof is that when interesting things
come along, you can go down that road and check it out.
This page describes some research that does not fall into my
mainstream interests.
Viterbi Decoding
Viterbi Decoding is a technique for decoding convolutional codes.
In this work, we were particularly interested in developing a new
architecture [1,2,3]
that could handle long constraint length codes, such as
the one that was to be used on the Galileo space probe.
We also did several implementations of the
architecture [4,5,6].
Arithmetic Coding
This is a technique for data compression.
Our interests are mostly in terms of architectures for VLSI
implementations [7,8,9,10]
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Gennady Feygin.
A Multiprocessor Architecture for Viterbi Decoders with Linear
Speed-up.
Master's thesis, University of Toronto, Department of Electrical
Engineering, Toronto, Ontario, M5S 3G4, 1990.
Co-supervised with Glenn Gulak.
Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
Generalized Cascade Viterbi Decoder--A Locally Connected
Multiprocessor with Linear Speed-Up.
In International Conference on Acoustics, Speech, and Signal
Processing, pages 1097-1100, Toronto, May 1991.
paper.pdf
(612785)
.
Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
A Multiprocessor Architecture for Viterbi Decoders with Linear
Speed-Up.
IEEE Transactions on Signal Processing, 41(9):2907-2917,
September 1993.
paper.pdf
(960806)
.
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin
Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, and Steve Wilton.
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
In 1993 IEEE International Symposium on Circuits and Systems,
pages 1945-1948, May 1993.
paper.pdf
(355733)
.
David Chun-Chin Yeh.
A Multiprocessor Viterbi Decoder Using Xilinx FPGAs.
Master's thesis, University of Toronto, Department of Electrical and
Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
thesis.ps.gz
(196452)
.
Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Error and VLSI Complexity in the Multiplication Free
Approximation of Arithmetic Coding.
In Data Compression Conference DCC '93, pages 118-127. IEEE,
March 1993.
paper.pdf
(387990)
.
Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Architectural Advances in the VLSI Implementation of Arithmetic
Coding for Binary Image Compression.
In Data Compression Conference DCC '94, pages 254-263. IEEE,
March 1994.
paper.pdf
(443679)
.
Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Excess Code Length and VLSI Complexity in the
Multiplication Free Approximation of Arithmetic Coding.
Journal of Information Processing and Management: Special Issue
on Data Compression, 30(6):805-816, 1994.
Gennady Feygin.
Arithmetic Coding: Algorithms and VLSI Architectures.
PhD thesis, University of Toronto, Department of Electrical and
Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
Co-supervised with Glenn Gulak.