Assem Bsoul
University of British Columbia
March, 2012
Leakage power is an important component of the total power consumption in FPGAs built using 90 nm and smaller technology nodes. Power gating, in which regions of the chip can be powered down when not used, has been shown to be effective at reducing leakage power. However, previous techniques focus on statically-controlled power gating. In this talk, we propose a modification to the fabric of an FPGA that enables dynamically-controlled power gating, in which logic clusters can be selectively powered down at run-time when they are idle. For applications containing blocks with large idle times, this could lead to significant leakage power savings. Our architecture utilizes the existing routing fabric and unused input pins of logic clusters to route the power control signals. We study the area and power tradeoffs by varying the basic architecture parameters of an FPGA. We also study the possible leakage energy savings using a model that characterizes an application in terms of its structure and behaviour.