Octavo: an FPGA-Centric Processor Family

Eric LaForest

University of Toronto

February, 2012

Overlay processor architectures allow FPGAs to be programmed by non-experts
using software, but prior designs have mainly been based on the architecture of
their ASIC predecessors.  In this talk (to appear in FPGA 2012) we present a
new processor architecture that from the beginning accounts for and exploits
the predefined widths, depths, maximum operating frequencies, and other
discretizations and limits of the underlying FPGA components.  The result is
Octavo, a ten-pipeline-stage eight-threaded processor that operates at the
block RAM maximum of 550MHz on a Stratix IV FPGA.  Octavo is highly
parameterized, allowing the exploration of trade-offs in datapath and memory
width, memory depth, and number of supported thread contexts.