Jeff Cassidy
University of Toronto
Jan 2014
One constant at FPGA conferences is complaints about the languages and synthesis tools used for FPGA designs. At the same time, high-level synthesis is a very active area both in research and industry. Designers want a language that is simple, clear, compact, area-efficient, high-performance, and easily debugged, but also promotes correct, robust, composable, reusable designs. Bluespec is a relatively new company founded out of MIT in 2003 that does a good job of addressing these concerns, particularly for control-intensive tasks.
This presentation gives an informal introduction to Bluespec SystemVerilog (BSV) from a hardware designer's perspective: what it is, what makes it different from other HLS, what advantages and limitations it has. I argue that Bluespec is to RTL as C++ is to assembly language: it offers powerful and expressive abstractions and supports code reuse while still allowing the designer very fine-grained control if desired. I also discuss my experiences going from a complete BSV beginner to using it for my entire MASc thesis project.