Skills

Digital Design

For ASICs & FPGAs

Software Development

C/C++, Python & more!

Teaching & Tutoring

is fun (seriously)

Experience

 
 
 
 
 
June 2018 – October 2018
Santa Clara, California

Research Scientist Intern

Intel

Responsibilities:

  • Investigated architecture and applications for next generation domain-specific embedded FPGAs.
  • Adapted existing internal EDA tooling for use with FPGA soft IP (bitstream generation, programmatic RTL generation).
  • Performed in depth analysis of machine learning FPGA accelerator overlays to evaluate potential architecture changes.
 
 
 
 
 
May 2015 – August 2016
Markham, Ontario

Standard Cell Engineering Intern

AMD

Responsibilities:

  • Improved existing software testing infrastructure ( extbf{Python, Perl}) in conjunction with other teams. Wrote extensive documentation as part of an internal quality initiative.&
  • Handled build, QA and release of 3rd Party Standard Cell IP for the first generation of external standard cell IP at AMD.
  • Performed various physical design tasks (e.g. characterization, technology migration, layout and schematic tweaks).

Recent Publications

Contact

  • PT477, D.L. Pratt Building, University of Toronto, Toronto, Canada M5S 3H5