Instruction Set Architecture
The supersmall processor supports a mostly-complete subset of the MIPS-I instruction set. For a complete reference to the instruction set, try reading SGI's documentation on the MIPS-IV instruction set, and ignore anything that doesn't apply to MIPS-I.
Supported | Unsupported |
---|---|
add | div |
addu | divu |
addi | lwl |
addiu | lwr |
and | mfhi |
andi | mflo |
beq | mthi |
bgez | mtlo |
bgtz | mult |
blez | multu |
bltz | swl |
bne | swr |
break | |
j | |
jal | |
jalr | |
jr | |
lb | |
lbu | |
lh | |
lhu | |
lui | |
lw | |
mfc0 | |
mtc0 | |
nor | |
or | |
ori | |
rfe | |
sb | |
sh | |
slt | |
sltu | |
slti | |
sltiu | |
sw | |
sll | |
sllv | |
sra | |
srav | |
srl | |
srlv | |
sub | |
subu | |
syscall | |
xor | |
xori |
Supported
- Basic operations: Addition, subtraction, shifting
- All branching and jumping instructions
- Aligned load and store operations
- Coprocessor operations: swc0 and lwc0
- Direct exception causing operations: break and syscall.
Unsupported
- Multiplication and division (mult, div)
- Floating point operations (add.s, mul.s)
- Unaligned loads and stores (lwl, swr)
- Non MIPS-I instructions (eret, beql)
A table listing all supported and some unsupported instructions is contained at the side of this page. If an instruction is not contained in the table, assume it to be unsupported.
A C/C++ compiler based on GCC is available from the download page that fully supports this instruction set.