News
- Nov 21, 2009: Fixed a problem with the download/registration page. If you were getting a POST error before, it should be working now. (Feel free to email us if this happens again)
- Sept 8, 2009: supersmall-2.0 released! Website documentation updated as well.
- August 12, 2009: supersmall-1.0 released! Get it from the download page.
Purpose
How small can you make a usable soft processor? That's what the supersmall soft processor is all about: take an easily-targetable 32-bit mostly MIPS-I compliant soft processor, and shrink it as far as you possibly can.
And how do you do that? Serialize. For example, need to add two 32-bit numbers? Well, you can do that in one of two ways: make a 32-bit adder that does all 32 additions at once, or make a 1-bit adder, and run it 32 times. The same technique applies to multiplexers: the more wires you're multiplexing, the more logic hardware it takes to implement. By doing everything one bit at a time, you significantly reduce the amount of hardware required.
Of course, this also makes the processor significantly slower. But if you cared about speed, you'd be doing it in hardware anyway, right?
Features
- Small - 207 Stratix III ALMs (Adaptive Logic Modules) maximum, and can be configured down to 115
- Configurable - exceptions support can be gradually disabled, decreasing size at the expense of features
- Written in pure synthesizable Verilog
- Mostly MIPS-I compliant
- Avalon memory mapped master, fully compatible with Altera's SOPC builder.
- Has been verified to work on actual hardware
- Freely downloadable and available under the 2-clause BSD license
Disadvantages
- Slow
- Has not been ported to non-Altera FPGAs
- Testing infrastructure is based on the rather expensive Terasic DE3.
- No MMU (can't run an operating system)
- Harvard architecture
So, if that's caught your interest, download it, check out the documentation, read about the hardware design, and use it whenever you need to add a supersmall soft processor to your FPGA designs.