[J21] C. Ting*, J. Liang*, A. Sheikholeslami, M. Kibune, H. Tamura,
A Blind Baud-Rate ADC-Based CDR
IEEE Journal of Solid-State Circuits,
Vol. 48, No. 12, pp. 3285-3295, Dec. 2013.
[C34] M. S. Jalali*, C. Ting*, B. Abiri*, A. Sheikholeslami, M. Kibune, H. Tamura,
A 3x Blind ADC-Based Receiver,
IEEE Asian Solid-State Circuits Conference (ASSCC),
Dig. Of Tech. Papers, pp. 1-4, to appear Nov. 2013.
[C33] M. S. Jalali*, R. Shivnaraine*, A. Sheikholeslami, M. Kibune, H. Tamura,
An 8mW Frequency Detector for 10Gb/s Half-Rate CDR using Clock Phase Selection,
IEEE Custom Integrated Circuit Conference (CICC),
Proceedings, pp. 1-4, Sep. 2013.
[C32] A. Sheikholeslami and H. Tamura,
Design Metrics for Blind ADC-Based Wireline Receivers (Invited Paper),
IEEE Custom Integrated Circuit Conference (CICC),
Proceedings, pp. 1-4, Sep. 2013.
[C31] C. Ting*, J. Liang*, A. Sheikholeslami, M. Kibune, H. Tamura,
A Blind Baud-Rate ADC-Based CDR,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 122-123, Feb. 2013.
[J19] B. Abiri*, A. Sheikholeslami, H. Tamura, and M. Kibune,
An Adaptation Engine for a 2x Blind ADC-Basead CDR in 65 nm CMOS
IEEE Journal of Solid-State Circuits,
Vol. 46, No. 12, pp. 3140-3149, Dec. 2011.
[C30] B. Abiri*, R. Shivnaraine*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 154-155, Feb. 2011.
[C29] B. Abiri*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 5Gb/s Adaptive DFE for 2x Blind ADC-Based CDR in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 436-437, Feb. 2011.
[C28] S. Shahramian*, C. Ting*, A. Sheikholeslami, H. Tamura, M. Kibune,
A Pattern-Guided Adaptive Equalizer in 65nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 354-355, Feb. 2011.
[C27] T. Tahmoureszadeh*, S. Sarvari*, A. Sheikholeslami, H. Tamura, Y. Tomita, M. Kibune,
A Combined Anti-Aliasing Filter and 2-tap FFE in 65-nm CMOS for 2x Blind 2-10 Gb/s ADC-Based Receivers
IEEE Custom Integrated Circuit Conference (CICC),
Proceedings, pp. 1-4, Sep. 2010.
[J18] O. Tyshchenko*, A. Sheikholeslami, H. Tamura, M. Kibune, H. Yamaguchi, and
J. Ogawa,
A 5Gb/s ADC-Based Feed-Forward CDR in 65nm CMOS
IEEE Journal of Solid-State Circuits,
Vol. 45, No. 6, pp. 1091-1098, June. 2010.
[C26] S. Sarvari*, T. Tahmoureszadeh*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS,
IEEE Symposium on VLSI Circuits,
Dig. of Tech. Papers, pp. 69-70, June 2010.
[C24] O. Tyshchenko*, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, T. Yamamoto,
A Fractional-Sampling-Rate ADC-Based CDR with Feed-Forward Architecture in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 166-167, Feb. 2010.
[C23] H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, S. Ohmoto, K. Tateishi,
O. Tyshchenko*, A. Sheikholeslami, T. Higuchi, J. Ogawa, T. Saito, H. Ishida, K. Gotoh,
A 5-Gb/s Transceiver with an ADC-Based Feed-Forward CDR and CMA Adaptive Equalizer in 65-nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Tech. Papers, pp. 168-169, Feb. 2010.
[C21] S. McLeod*, A. Sheikholeslami, T. Yamamoto, N. Nedovic, H. Tamura, and W. W. Walker,
A Digital Offset-Compensation Scheme for an LA and CDR in 65-nm CMOS,
IEEE Symposium on VLSI Circuits,
Dig. of Tech. Papers, pp. 448-449, June 2009.
[J16] M. van Ierssel*, H. Yamaguchi, A. Sheikholeslami, H. Tamura, and W. W. Walker,
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI,
IEEE Trans. on Circuits and Systems I :Regular Papers,
Vol. 55, No. 5, pp. 1306-1315, June 2008.
[J15] M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 3.2Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance,
IEEE Journal of Solid-State Circuits,
pp. 2224-2234, October 2007.
[C20] R. Yuen*, M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers,
IEEE Custom Integrated Circuit Conference (CICC),
Proceedings, pp. 413-416, Sep. 2006.
[C19] M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 3.2Gb/s Semi-Blind-Oversampling CDR,
IEEE International Solid-State Circuits Conference (ISSCC),
Digest of Technical Papers, pp. 334-335, Feb. 2006.
For a complete list of publications, please refer to Publications and Patents
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