Patents

  1. (Patent Filed 2007, Issued 2013) Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices. 8589849. 2008-01-01. A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints.

  2. (Patent Filed 2007, Issued 2012) M/A for performing incremental compilation using top-down and bottom-up design approaches. 8589838. 2008-01-01. A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

  3. (Patent Filed 2006, Issued 2013) Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches. 7669157. 2008-01-01. A method for designing a system on a target device including merging netlists for first and second partitions of the system, and performing fitting on the combined netlist.

  4. (Patent Filed 2008, Issued 2012) Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis. 8296696. 2008-01-01. A method for designing a system on a target device includes synthesizing the system.

  5. (Parent Filed 2009, Issued 2012) Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches. 8250505. 2008-01-01. A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

  6. (Patent Filed 2007, Issued 2012) Methods for instruction trace decomposition. 8095914. 2008-01-01. An instruction trace is segmented into a number of contiguous instruction segments, such that each boundary between adjacent instruction segments is defined by a branch instruction. A segment identifier is assigned to each instruction segment, such that each instruction segment having identical content is assigned a same segment identifier. Using the assigned segment identifiers, the instruction trace is translated into a sequence of segment identifiers. The sequence of segment identifiers is then iteratively consolidated into a prime form that does not include a repetition of a heterogeneous pair of consecutive segment identifiers. The prime form of the sequence of segment identifiers is then rendered in a graphical format.

  7. (Patent Filed 2007, Issued 2011) Method and apparatus for performing multiple stage physical synthesis. 7996797. 2008-01-01. A method for designing a system on a target device includes entering 11 the system.

  8. (Patent Filed 2006, Issued 2009) Method and apparatus for performing post-placement routability optimization. 7620925. 2008-01-01. A method for designing a system on a target device includes synthesizing the system.

  9. (Patent Filed 2003, Issued 2009) Method and apparatus for performing layout-driven optimizations on field programmable gate arrays. 7594204. 2008-01-01. Method for designing a system on a target device using field programmable gate arrays

  10. (Patent Filed 2007, Issued 2009) Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines. 7500216. 2008-01-01. Method for designing a system on a target device including synthesizing the system.

  11. (Patent Filed 2006, Issued 2008) Method and apparatus for performing incremental compilation. 7464362. 2008-01-01. A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist.

  12. (Patent Filed 2006, Issued 2008) Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays. 7318210. 2008-01-01. A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes placing new logic elements (LEs) at preferred locations on a layout of an existing system.

  13. (Patent Filed 2002, Issued 2007) Method and apparatus for designing systems using logic regions. 7197734. 2008-01-01. Method for positioning components of a system onto a target device utilizing programmable logic devices.

  14. (Patent Filed 2003, Issued 2007) Method and apparatus for implementing soft constraints in told used for designing system on programmable logic devices. 7194720. 2008-01-01. Method for designing a system on a target device utilizing programmable logic devices.

  15. (Patent Filed 2002, Issued 2004) Method and apparatus for placement of components onto programmable logic devices. 6779169. 2008-01-01. Method for positioning components of a system onto a target device using programmable logic devices.

Books

  1. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design. 3: 850 pages, McGraw-Hill, 2013

  2. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design. 3: 945 pages, McGraw-Hill, 2009

  3. Stephen Brown, Robert Francis, Jonathan Rose, and Zvonko Vranesic, Field-Programmable Gate Arrays, Springer, 1992.

Book Chapters

  1. A. Canis, J. Choi, B. Fort, B. Syrowik, R.L. Lian, Y.-T. Chen, H. Hsiao, J. Goeders, S. Brown, J.H. Anderson, LegUp high-level synthesis, Ed. D. Koch, F. Hannig, D. Ziener. FPGAs for Software Engineers, 175-190, Springer, 2015.

  2. Plavec, Franjo and Vranesic, Zvonko and Brown, Stephen, Stream programming for FPGAs, Ed. Radetzki Martin, Languages for Embedded Systems and Their Applications, 241-253, Springer, 2009.

Journal Papers

  1. R. Nane, V.-M. Sima, F. Ferrandi, C. Pilato, J. Choi , B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, J.H. Anderson, Koen Bertels, "A survey and evaluation of FPGA high-level synthesis tools," accepted to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), November 2015.

  2. Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J.H. Anderson, "The effect of compiler optimizations on high-level synthesis-generated hardware," ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 8, no. 3, May, 2015.

  3. Canis, Andrew and Choi, Jongsok and Aldham, Mark and Zhang, Victor and Kammoona, Ahmed and Czajkowski, Tomasz and Brown, Stephen D and Anderson, Jason H, "LegUp: An opensource high-level synthesis tool for FPGA-based processor/accelerator systems," ACM Transactions on Embedded Computing Systems (TECS). 13(2): 24, 2013.

  4. Plavec, Franjo and Vranesic, Zvonko and Brown, Stephen, "Exploiting Task-and Data-Level Parallelism in Streaming Applications Implemented in FPGAs," ACM Transactions on Reconfigurable Technology and Systems (TRETS). 6(4): 16., 2013

  5. Ling, Andrew C and Brown, Stephen Dean and Safarpour, Sean and Zhu, Jianwen, "Toward Automated ECOs in FPGAs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 30(1): 18--30, 2011.

  6. Czajkowski, Tomasz S and Brown, Stephen D., "Decomposition-based vectorless toggle rate computation for FPGA circuits," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 29(11): 1723--1735, 2010.

  7. Ling, Andrew C and Zhu, Jianwen and Brown, Stephen Dean, "Scalable synthesis and clustering techniques using decision diagrams," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 27(3): 423--435, 2008

  8. Czajkowski, Tomasz S and Brown, Stephen Dean, "Functionally linear decomposition and synthesis of logic circuits for FPGAs," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 27(12): 2236--2249, 2008

  9. A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 26, No 7, July 2007, pp. 1196-1210

  10. A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 26, No 7, July 2007, pp. 1196-1210.

  11. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Predicting Interconnect Delay for Physical Synthesis in an FPGA CAD Flow", IEEE Transactions on Very Large Scale Integration Systems, Volume 15, Number 8, August 2007, pp. 895-903.

  12. Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 11, November 2006, pp. 2331-2340.

  13. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Predicting Interconnect Delay for Physical Synthesis in an FPGA CAD Flow", IEEE Transactions on Very Large Scale Integration Systems, Volume 15, Number 8, August 2007, pp. 895-903

  14. Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 25, No. 11, November 2006, pp. 2331-2340.

  15. Andrew C. Ling, Deshanand P. Singh and Stephen D. Brown, "FPGA PLB Evaluation using Quantified Boolean Satisfiability," in IEE Proceedings on Computers and Digital Techniques, Volume 153, Number 3, May 2006, pp. 165-172. ISSN 1350-2387 Invited Journal Paper

  16. Deshanand P. Singh and Stephen D. Brown, "An Area-Efficient Timing Closure Technique for FPGAs using Shannon's Expansion," The Integration, VLSI Journal special issue on VLSI System-On-Chip, pp. 41-50, 2003.

  17. Alireza Kaviani and Stephen D. Brown, "The Hybrid Field-Programmable Architecture," IEEE Design and Test of Computers, April-June 1999, pp. 74-83.

  18. Stephen D. Brown, "FPGA Architectural Research: A Survey," IEEE Design and Test of Computers, Vol. 13, No. 4, 1996, pp. 9-15.

  19. Stephen D. Brown, Muhammad Khellah, and Zvonko Vranesic, "Minimizing FPGA Interconnect Delays," IEEE Design and Test of Computers, Vol. 13, No. 4, 1996, pp. 16-23.

  20. Stephen D. Brown and Jonathan Rose, "FPGA and CPLD Architectures: A Tutorial," IEEE Design and Test of Computers, Vol. 13, No. 2, 1996, pp. 42-57.

  21. Stephen D. Brown, Guy Lemieux, and Muhammad Khellah, "Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays," Journal of VLSI Design, Vol. 4, No. 4, 1996, pp. 275-291.

  22. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol 12, No. 12, Dec. 1993, pp 1827-1838.

  23. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol 12, No. 12, Dec. 1993, pp 1827-1838.

  24. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol. 11, No. 5, May 1992, pp. 620-628.

  25. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE Transactions on Computer Aided Design of Integrated Circuits and System, Vol. 11, No. 5, May 1992, pp. 620-628.

  26. Jonathan Rose and Stephen D. Brown, "Flexibility of Interconnection Structures in Field-Programmable Gate Arrays," IEEE Journal of Solid State Circuits, Vol. 26, No. 3, March 1991, pp. 277-282.

  27. Stephen D. Brown and Zvonko Vranesic, "A Chip for Fault Detection Experiments," Journal of Semi-Custom ICs, Vol. 7, No. 5, 1990, pp. 48-50.

Conference Papers

  1. J. Choi, S. Brown, J. Anderson, "Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware," IEEE Int'l Conference on Field- Programmable Technology (FPT), New Zealand, 2015-12-18

  2. A. Canis, J.H. Anderson, S.D. Brown, "Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis," IEEE International Conference on Field-Programmable Logic and Applications (FPL), Munich, Germany, 2014-09-04

  3. N. Calagar, S. Brown, J.H. Anderson, "Source-Level debugging for FPGA high-Level synthesis," IEEE International Conference on Field-Programmable Logic and Applications (FPL), Munich, Germany, 2014-09-04

  4. B. Fort, A. Canis, J. Choi, N. Calagar, R. Lian, S. Hadjis, Y.T. Chen, M. Hall, B. Syrowik, T. Czajkowski, S.D. Brown, J.H. Anderson, "Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis," Proceedings of International Conference on Embedded and Ubiquitous Computing (EUC), Milan, Italy, 2014-08-25

  5. Czajkowski, Tomasz S and Neto, David and Kinsner, Michael and Aydonat, Utku and Wong, Jason and Denisenko, Dmitry and Yiannacouras, Peter and Freeman, John and Singh, Deshanand P and Brown, Stephen D., "OpenCL for FPGAs: Prototyping a Compiler. Proceedings of Engineering of Reconfigurable Systems and Algorithms," Engineering of Reconfigurable Systems and Algorithms, Las Vegas, United States, 2013-07-18

  6. Choi, Jongsok and Brown, Stephen and Anderson, Jason, "From software threads to parallel hardware in high-level synthesis for FPGAs," Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, 2013-12-09 (270--277)

  7. Cai, Jiu Cheng and Lian, Ruolong and Wang, Mengyao and Canis, Andrew and Choi, Jongsok and Fort, Blair and Hart, Eric and Miao, Emily and Zhang, Yanyan and Calagar, Nazanin, "From C to Blokus Duo with LegUp high-level synthesis," Proceedings of the IEEE International Conference on Field-Programmable Technology (FTP), Kyoto, Japan, 2013-12-09 (486--489)

  8. Canis, Andrew and Choi, Jongsok and Fort, Blair and Lian, Ruolong and Huang, Qijing and Calagar, Nazanin and Gort, Marcel and Qin, Jia Jun and Aldham, Mark and Czajkowski, Tomasz, "From software to accelerators with LegUp high-level synthesis," IEEE International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Montreal, Canada, 2013-09-30 (1-18)

  9. Huang, Qijing and Lian, Ruolong and Canis, Andrew and Choi, Jongsok and Xi, Ryan and Brown, Stephen and Anderson, Jason, "The effect of compiler optimizations on high-level synthesis for FPGAs," IEEE International Conference on Field-Programmable Custom Computing Machines (FCCM), Seattle, United States, 2013-04-29 (89--96)

  10. Canis, Andrew and Anderson, Jason H and Brown, Stephen D., "Multi-pumping for resource reduction in FPGA high-level synthesis," Conference on Design, Automation and Test in Europe (DATE), Grenoble, France, 2013-03-18 (194--197)

  11. Hadjis, Stefan and Canis, Andrew and Anderson, Jason H and Choi, Jongsok and Nam, Kevin and Brown, Stephen and Czajkowski, Tomasz, "Impact of FPGA architecture on resource sharing in high-level synthesis," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, United States, 2013-02-14 (111--114)

  12. Choi, Jongsok and Nam, Kevin and Canis, Andrew and Anderson, Jason and Brown, Stephen and Czajkowski, Tomasz, "Impact of cache architecture and interface on performance and area of FPGA-based processor/parallel-accelerator systems," IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, 2012-04-30 (17--24)

  13. Aldham, Mark and Anderson, Jason and Brown, Stephen and Canis, Andrew, " Low-cost hardware profiling of run-time and energy in FPGA embedded processors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Santa Monica, United States, 2011-09-12 (61--68)

  14. Canis, Andrew and Choi, Jongsok and Aldham, Mark and Zhang, Victor and Kammoona, Ahmed and Anderson, Jason H and Brown, Stephen and Czajkowski, Tomasz, "LegUp: high-level synthesis for FPGA-based processor/accelerator systems," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, United States, 2011-02-15 (33--36)

  15. Betz, Vaughn and Brown, Stephen, "FPGA challenges and opportunities at 40nm and beyond," International Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA), Las Vegas, United States, 2010-07-19 (1-4)

  16. Plavec, Franjo and Vranesic, Zvonko and Brown, Stephen, "Enhancements to FPGA design methodology using streaming," IEEE International Conference on Field-Programmable Logic and Applications (FPL), Prague, Czech Republic, 2009-08-31 (294--301)

  17. Czajkowski, T.S. and Brown, S.D., "Fast toggle rate computation for FPGA circuits," IEEE International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008-09-08 (65--70)

  18. Plavec, Franjo and Vranesic, Zvonko and Brown, Stephen, "Towards compilation of streaming programs into FPGA hardware," IEEE Conference on Specification, Verification and Design Languages (FDL), Stuttgart, Germany, 2008-09-23 (67--72)

    19. Ling, Andrew C and Zhu, Jianwen and Brown, Stephen D., "Delay driven AIG restructuring using slack budget management," ACM 18th Great Lakes symposium on VLSI, Houston, United States, 2008-05-20 (163--166)
  19. Manohararajah, Valavan and Chiu, Gordon R. and Singh, Deshanand P. and Brown, Stephen D., "Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow," ACM/IEEE International Workshop on System-level Interconnect (SLIP), Munich, Germany, 2006-03-04 (3--8)

  20. Singh, Deshanand P and Manohararajah, Valavan and Brown, Stephen D, "Two-stage physical synthesis for FPGAs," Custom Integrated Circuits Conference (CICC), San Jose, United States, 2005-09-18 (171--178)

  21. Manohararajah, Valavan and Singh, Deshanand P and Brown, Stephen Dean, "Postplacement BDD-based decomposition for FPGAs," IEEE International Conference on Field-Programmable Logic (FPL), Tampere, Finland, 2005-08-24 (31--38)

  22. Singh, Deshanand P. and Manohararajah, Valavan and Brown, Stephen D., "Incremental Retiming for FPGA Physical Synthesis," IEEE Design Automation Conference (DAC), San Diego, United States, 2005-06-13 (433--438)

  23. Ling, Andrew and Singh, Deshanand P and Brown, Stephen D., "FPGA technology mapping: a study of optimality," IEEE Design Automation Conference (DAC), San Diego, United States, 2005-06-13 (427--432)

  24. F. Plavec, Z. G. Vranesic, Stephen D. Brown, "On Digital Search Trees: A Simple Method for Constructing Balanced Binary Trees", in Proceedings of the 2nd International Conference on Software and Data Technologies (ICSOFT '07), vol. 1, Barcelona, Spain, July, 2007, pp. 61-68.

  25. Andrew C. Ling, Deshanand P. Singh, and Stephen D.Brown, "Incremental Placement for Structured ASICs using the Transportation Problem", in Proceedings of the 2007 International Conference of Very Large Scale Integration (VLSI-SoC), Atlanta, Georgia, USA, Oct 2007, pp. 172-177.

  26. Tomasz Czajkowski and Stephen D. Brown, "Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits," proceedings of the 44th Design Automation Conference, San Diego, California, June 4-8, 2007, pp. 324-329.

  27. Andrew Ling, Jianwen Zhu, Stephen D. Brown, "BddCut: Towards Scalable Symbolic Cut Enumeration," in ASP-DAC'07: Proceedings of the 2007 conference on Asia South Pacific Design Automation, Yokohama, Japan, Jan 2007, pp 408-413.

  28. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "Mapping Arbitrary Logic Functions into Synchronous Embedded Memories for Area Reduction on FPGAs", Proceedings of the International Conference on Computer-Aided Design, San Jose, California, November 2006, pp. 135-142.

  29. Blair Fort, Davor Capalija, Zvonko G. Vranesic, and Stephen D. Brown, "A Multithreaded Soft Processor for SoPC Area Reduction," in Proceedings of IEEE International Symposium on Custom Computing Machines, Napa, CA, October 2006, pp. 131-142.

  30. Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Adaptive FPGAs: High-Level Architecture and a Synthesis Method", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 267-274.

  31. Mehrdad Eslami Dehkordi, Stephen D. Brown, Terry Borer, "Modular Partitioning for Incremental Compilation", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 113-118.

  32. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, and Stephen D. Brown, "Difficulty of Predicting Interconnect Delay in a Timing Driven FPGA CAD Flow", In Proceedings of the Workshop on System Level Interconnect Prediction, Munich, Germany, March 2006, pp. 3-8.

  33. Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Two-Stage Physical Synthesis for FPGAs", invited double-length paper in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2005, pp. 171-178.

  34. Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Two-Stage Physical Synthesis for FPGAs", invited double-length paper in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2005, pp. 171-178.

  35. Deshanand Singh, Valavan Manohararajah, and Stephen D. Brown, "Incremental Retiming for FPGA Physical Synthesis", Proceedings of the 42nd Design Automation Conference (DAC'05), Anaheim, CA, June 2005, pp. 433-438.

  36. Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Timing-Driven Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 415-422.

  37. A. C. Ling, D. P. Singh, Stephen D. Brown, "FPGA technology mapping: a study of optimality", nominated for best paper in Proceedings of the 42nd Design Automation Conference (DAC05), pp 427-432, Anaheim, CA, June 2005.

  38. Andrew C. Ling, Deshanand P. Singh, Valavan Manohararajah, and Stephen D. Brown, "FPGA Architecture Evaluation and Technology Mapping using Boolean Satisfiability", in Proceedings of the International Workshop on Logic and Synthesis, Lake Arrowhead, CA, June 2005, pp. 399-406.

  39. A.C. Ling, D.P.Singh, and Stephen D. Brown, "FPGA Logic Synthesis using Quantified Boolean Satisfiability", in SAT '05: The 7th International Conference on Theory and Applications of Satisfiability Testing, St. Andrews, Scotland, June 2005, pp. 444-450.

  40. A.C.Ling, D.P.Singh, and Stephen D. Brown, "FPGA PLB Evaluation using Quantified Boolean Satisfiability," Proceedings of Field-Programmable Logic (FPL05), Finland, Aug 2005, pp. 25-29.

  41. Franjo Plavec, Blair Fort, Zvonko Vranesic, and Stephen D. Brown, "Experiences with Soft-Core Processor Design," 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, CO, April 2005, pp. 167-170.

  42. V. Manohararajah, Stephen D. Brown, and Z. Vranesic. "Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping". In Proceedings of the International Workshop on Logic and Synthesis, Temecula, California, USA, June 2004, pp. 14-21.

  43. Valavan Manohararajah, Deshanand P. Singh, and Stephen D. Brown, "Post-Placement Functional Decomposition for FPGAs", in Proceedings of the International Workshop on Logic and Synthesis, Temecula, CA, June 2004, pp. 114-118.

  44. Mehrdad Eslami Dehkordi and Stephen D. Brown, "Performance-Driven Recursive Multi-level Clustering," FPT.2003, Tokyo, Japan, December, 2003, pp. 262-269.

  45. Karl Schabas and Stephen D. Brown, "Using Logic Duplication to Improve Performance in FPGAs," FPGA.03, Monterey, CA, February, 2003, pp. 136-142.

  46. Deshanand Singh and Stephen D. Brown, "An Area-Efficient Timing-Closure Technique for FPGAs using Shannon's Expansion," International Conference on VLSI, Las Vegas, NV, February 2003.

  47. Deshanand Singh, Terry Borer, Stephen D. Brown, "Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices," International Conference on VLSI, Las Vegas, NV, February 2003.

  48. Mehrdad Dehkordi and Stephen D. Brown, "The Effect of Cluster Packing and Node Duplication Control in Delay-driven Clustering," FPT.02, Hong Kong, December, 2002, pp. 227-233.

  49. Valavan Manohararajah, Terry Borer, Stephen D. Brown, and Zvonko G. Vranesic, "Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices", in Proceedings of the Conference on Field-Programmable Logic and Applications, Montpelier, France, September 2002, pp. 232-241.

  50. Deshanand Singh and Stephen D. Brown, "Incremental Placement for Layout-Driven Optimizations in FPGAs," ICCAD, San Jose, CA, June. 2002, pp. 752-760.

  51. Deshanand Singh and Stephen D. Brown, "Integrated Retiming and Placement for Field Programmable Gate Arrays," International Symposium on FPGAs (FPGA.2002), Monterey, CA, Feb 2002, pp. 67-76.

  52. Deshanand Singh and Stephen D. Brown, "Constrained Clock Shifting for Field Programmable Gate Arrays," International Symposium on FPGAs (FPGA.2002), Monterey, CA, Feb 2002, pp. 121-126.

  53. Deshanand Singh and Stephen D. Brown, "The Case for Registered Routing Switches in Field Programmable Gate Arrays," International Symposium on FPGAs, Feb 2001, pp. 161-169.

  54. R. Grindley, T. Abdelrahman, Stephen D. Brown, et. al., "The NUMAchine Multiprocessor," International Conference on Parallel Processing, Sept. 2000, pp. 487-496.

  55. Alireza Kaviani and Stephen D. Brown, "Technology Mapping Issues for an FPGA with Lookup Tables and PLA-like blocks," International Symposium on FPGAs, Monterey, California, Feb 2000, pp. 60-66.

  56. Jason Anderson and Stephen D. Brown, "Technology Mapping for Large CPLDs," IEEE Design Automation Conference, San Francisco, June 1998, pp. 698-703.

  57. Alex Grbic, Stephen D. Brown, Steve Caranci, Robin Grindley, Mitch Gusat, Guy Lemieux, Kelvin Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko Vranesic and Zeljko Zilic, "The Design and Implementation of the NUMAchine Multiprocessor," IEEE Design Automation Conference, San Francisco, June 1998, pp. 66-69.

  58. Alireza Kaviani, Daniel Vranesic and Stephen D. Brown, "The Computational FPGA Architecture," IEEE Custom Integrated Circuits Conference, May 1998, Santa Clara, CA, May 1998, pp. 12.2.1-12.2.4.

  59. Jason Anderson and Stephen D. Brown, "An LPGA with Foldable PLA-Style Logic Blocks," FPGA.98, Monterey Bay, CA, February, 1997, pp. 244-252.

  60. Guy G.F. Lemieux, Stephen D. Brown and Daniel Vranesic, "On Two-Step Routing for FPGAs," ISPD, Napa Valley, CA, U.S.A., April 1997, pp 60-66.

  61. Stephen D. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic, and S. Srbljic, "Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools," IEEE Design Automation Conference, Las Vegas, June. 1996, pp. 427-432. This was nominated as a best paper.

  62. Alireza Kaviani and Stephen D. Brown, "Hybrid FPGA Architecture," FPGA.96, Monterey, CA, Feb. 1996, pp. 1-7.

  63. Stephen D. Brown, "An Overview of Technology, Architecture, and CAD Tools for Programmable Logic Devices," IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1994. This was a double-length invited paper, pp. 69-76.

  64. Stephen D. Brown, Muhammad Khellah, and Zvonko Vranesic, "Minimizing FPGA Interconnect Delays," IEEE Custom Integrated Circuits Conference, San Diego CA, May 1994, pp. 181-184.

  65. Muhammad Khellah, Stephen D. Brown, and Zvonko Vranesic, "Modeling Routing Delays in SRAM-based FPGAs," Canadian Conference on VLSI, Nov 1993, pp. 6B.13-6B.18.

  66. Ben Tseng, Jonathan Rose and Stephen D. Brown, "Using Architectural and CAD Interactions to Improve FPGA Routing Architectures," IEEE International Conference on Circuit Design, 1992, 6 pages.

  67. Stephen D. Brown, Jonathan Rose and Zvonko G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays," IEEE International Conference on Computer-Aided Design, Santa Clara, Nov 1990. This publication won a best paper award, pp. 382-385.

  68. Jonathan Rose and Stephen D. Brown, "Flexibility of Interconnection Structures in Field-Programmable Gate Arrays," IEEE Custom Integrated Circuits Conference, Boston, May 1990, pp. 27.5.1-27.5.4.

  69. Stephen D. Brown and Zvonko Vranesic, "A Chip for Fault Detection Experiments," Canadian Conference on VLSI, pp. 9-13, Vancouver, BC, Oct. 1989. This was nominated as a best paper.