Objective

Matrix is an electronic system level (ESL) design environment being developed at the University of Toronto. This project attempts to answer two basic questions. First, how can a system-on-chip (SOC) be programmed? Second, how can such a program be efficiently verified?

Background

The first question for the traditional computer systems was well answered: hundreds of programming languages have been devised for the general purpose desktop computers. The industrial practice seems to settle on C and its derivatives (C++, Java, or C#). The same question is difficult for SOCs, which are inherently heterogeneous: SOCs might contain generic processors (microcontrollers, RISCs), domain or application specific processors (DSP, Media processors, ASIPs), generic hardware cores (UART, GPIOs etc), and custom hardware cores. It is difficult to draw the boundary between application and architecture, and decide the programming models to be used on a machine that does not yet exist.

The second question was arguably manageable for the traditional computer systems: although software bugs proliferate, it is mainly due to the lack of quality control enforcement. At least software programs can be compiled and readily run against the test suites. Unfortunately one cannot run an SOC program when at the same time the SOC is being designed. This leaves one only with the options of formal verification, which does not yet scale, or simulation, which has to combine HDL based hardware simulator with instruction set based software simulators. The speed of today's simulators is slow enough for some to resort to million dollar hardware emulators. To make things worse, testbench generation, the dual problem of simulation, is difficult in the first place at the behavioral level. It is also difficult to carry such testbench forward to regression test the RTL and gate level implementation.

Ideas

We explore several ideas to approach the specification and verification problems in SOCs.

Context flow

One reason that accounts for the success of hardware description languages in RTL is that they are composable: one can construct hardware modules with well defined interfaces, or input and output ports, and by simply connecting ports of constituent modules, the behavior of a larger system can be implicitly defined. Recent advances in software architecture advocates software structures that mimic hardware, where software components are connected through abstract interfaces to form larger systems. Similar idea was employed in the SpecC language (and later SystemC), which extends data ports in HDLs with transaction level interfaces. To establish an SOC programming model at the behavioral level, our first idea is to develop a simple, declarative, pure component language, where the behavior of composite components are defined only by component connections, and the behavior of leaf components are specified in external, ``native'' languages such as C. The composition semantics dictates that component interaction is exclusively through context flow, and both sequential and parallel implementation are equally valid, making the process of hardware software partitioning extremely easy from both the user and the tool's perspective.

Hardware carrying code

To establish a programming model at the architectural level, our second idea is to establish an abstraction level that unifies both application software and hardware. The chosen abstraction is an extension of the familiar instruction set model, called hardware carry code (HCC). This unification enables the use of the optimization kernels for hardware synthesis and software compilation, and the co-verification of heterogeneous architectural components in a uniform manner.

Automated test and transactor synthesis

To automatically verify a component under design, we synthesize a testbench (or in the software world, a unit test suite) by using a combination of program instrumentation and formal verification techniques. The synthesized testbench ensures all or almost all program execution paths are covered. To enable regression test on RTL, we also synthesize transactors on modern transaction level simulation infrastructures.

Trace based dynamic compilation

To verify a complete application signoff, in the form of HCC, at high speed, we develop a fast, multiprocessor instruction set simulator using the dynamically compiled simulation. In particular, we emit native code on spots that profit speed, called hot traces, which normally correspond to loop bodies. In addition, the granularity of native code generation is extended across basic blocks, thus further improving speed.

Results

At ICCAD'04, we reported a trace based dynamically compiled simulator, called DynamoSim, which manages to achieve an average 5.28 time speed up on SPEC2000 benchmarks.

Publications

[1]      

Wai Sum Mong and Jianwen Zhu, ``DynamoSim: A trace-based dynamic compiled instruction set simulator,'' in Proceedings of the International Conference on Computer Aided Design (ICCAD), San Jose, California, November 2004.

[2]      

Wai Sum Mong and Jianwen Zhu, ``A retargetable simulator of micro-architecture,'' in Proceedings of the Design Automation Conference (DAC), Anaheim, California, June 2003.

[3]      

Wai Sum Mong, ``Retargetable binary tools for embedded software,'' M.S. thesis, Department of Electrical and Computer Engineering, University of Toronto, Toronto, Jan. 2004.

[4]      

Wai Sum Mong and Jianwen Zhu, ``Design and implementation of a retargetable linker,'' Tech. Rep. TR-04-02-03, Department of Electrical and Computer Engineering, University of Toronto, Apr. 2003.

[5]      

Wai Sum Mong and Jianwen Zhu, ``A hacker's guide to gnu binary utilities,'' Tech. Rep. TR-11-01-02, Department of Electrical and Computer Engineering, University of Toronto, Nov. 2002.

Related Past Publications

[1]      

Maghsoud Abbaspour and Jianwen Zhu, ``Retargetable binary utilities,'' in Proceedings of the Design Automation Conference (DAC), New Orleans, LA, June 2002.

[2]      

Maghsoud Abbaspour and Jianwen Zhu, ``Automatic porting of BFD library,'' in "International Workshop on System-on-Chip for Real-Time Applications (IWSOCRT), Banff, Canada, July 2002.

[3]      

Jianwen Zhu and Daniel D. Gajski, ``An ultra-fast instruction set simulator,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, June 2002.

[4]      

Jianwen Zhu and Daniel D. Gajski, ``Compiling SpecC for simulation,'' in Proceeding of Asia and South Pacific Design Automation Conference (ASPDAC), Pacifico Yokohama, Japan, January 2001.

[5]      

Jianwen Zhu and Daniel D. Gajski, ``A retargetable, ultra-fast instruction set simulator,'' in Proceedings of the Design Automation and Test Conference in Europe (DATE), Munich, Germany, March 1999.

[6]      

Daniel D. Gajski, Jianwen Zhu, and Rainer Dömer, SpecC: Specification Language and Methodology, Japanese Edition, CQ Publishing, Japan, December 2000.

[7]      

Daniel D. Gajski, Jianwen Zhu, and Rainer Dömer, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, Boston, March 2000.

[8]      

Jianwen Zhu, ``MetaRTL: Raising the abstraction level of RTL design,'' in Proceedings of the Design Automation and Test Conference in Europe (DATE), Munich, Germany, March 2001.

[9]      

Jianwen Zhu and Daniel D. Gajski, ``A unified formal model for ISA and FSMD,'' in International Workshop on Hardware/Software Codesign (CODES), Rome, Italy, May 1999.

[10]      

Jianwen Zhu and Daniel D. Gajski, ``OpenJ: An extensible system level design language,'' in Proceedings of the Design Automation and Test Conference in Europe (DATE), Munich, Germany, March 1999.

[11]      

Rainer Dömer, Daniel D. Gajski, and Jianwen Zhu, ``Specification and design of embedded systems,'' it+ti, , no. 3, June 1998.

[12]      

Jianwen Zhu, Rainer Dömer, and Daniel D. Gajski, ``Syntax and semantics of SpecC language,'' in Proceedings on the Seventh Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Japan, December 1997.

Contributors

Toronto Synthesis Group

Wai Sum Mong	Jianwen Zhu

Web

http://www.eecg.toronto.edu/~jzhu/matrix.html