Research |
My research interests are in systems architecture/design, and
reconfigurable devices. My graduate work has been in FPGA-based soft
processors and their customization. We've developed an infrastructure for
rapidly generating efficient RTL descriptions of a processor from an input
description. We've dubbed the system SPREE (Soft Processor Rapid
Exploration Environment) and more can be found about it by going to The SPREE Home Page. We've migrated SPREE to
real hardware connected to DDR SDRAM and found that our embedded benchmarks
are generally compute bound. Recently we've investigated adding vector
extensions to soft processors as a means of increasing their compute power
in a scalable and user-selectable way. For more information on this project please visit the The VESPA Home Page.
Theses Projects
- VESPA - FPGA-based soft vector processors
- SPREE - Microarchitecture exploration of FPGA-based soft processors
Supervisors
Journal Publications
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Peter Yiannacouras, Gregory J. Steffan, and Jonathan Rose, Portable, Flexible, and Scalable Soft Vector Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 99, No. 1, pp. 1-14 July 2011
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Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow, A Desktop Computer with a Reconfigurable Pentium, ACM Transactions on Reconfigurable Technology and Systems, Vol. 1, No. 1, pp. 5:1-5:15 March 2008 (pdf)
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Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Custom Code Generation for Soft Processors, SIGARCH Computer Architecture News, Vol. 35, No. 3, pp. 9-19, June 2007.
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Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Exploration and Customization of FPGA-Based Soft Processors, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 26, No. 2, pp. 266-277, February 2007 (pdf)
Refereed Conference Publications
- Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Fine-Grain Performance Scaling of Soft Vector Processors, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2009, Grenoble, France, pp. 97-106. (pdf ppt - Acceptance Rate 35%)
- Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Data Parallel FPGA Workloads: Software Versus Hardware, International Conference on Field-Programmable Logic and Application, Aug 2009, Prague, Czech Republic. (pdf ppt - Acceptance Rate 25%)
- Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2008, Atlanta, GA. (pdf ppt)
- Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, Scaling Soft Processor Systems, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Palo Alto, CA, April, 2008 (pdf - Acceptance Rate 28%)
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Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow, An FPGA-Based Pentium(R) in a Complete Desktop System, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2007, Monterey, CA. (pdf - Acceptance Rate 24%)
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Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Application-Specific Customization of Soft Processor Microarchitecture, ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2006, Monterey, CA. (pdf ppt - Acceptance Rate 22%)
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Peter Yiannacouras, Jonathan Rose, and J. Gregory Steffan, The Microarchitecture of FPGA-Based Soft Processors, International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), September 2005, San Francisco, CA. (pdf ppt - Acceptance Rate 31%)
Workshops
- Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Improving Memory Systems for Soft Vector Processors, Workshop on Soft Processor Systems (WoSPS - in conjunction with PACT), October 2008, Toronto, ON.(pdf ppt)
- Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Custom Code Generation for Soft Processors, Reconfigurable and Adaptive Architecture Workshop (RAAW - in conjunction with MICRO), December 2006, Orlando, FA.(pdf)
Posters
- Peter Yiannacouras, Jonathan Rose, and J. Gregory Steffan, SPREE: Microarchitectural Exploration on FPGAs, Workshop on Architecture Research using FPGA Platforms (WARFP - in conjunction with HPCA), February 2005, San Francisco, CA. (pdf ppt)
- Peter Yiannacouras and Jonathan Rose, A Parameterized Automatic Cache Generator for FPGAs, Field Programmable Technologies (FPT 2003), December 2003, Tokyo, Japan.
Theses
- Peter Yiannacouras, FPGA-Based Soft Vector Processors, PhD Thesis, University of Toronto, 2009. (pdf)
- Peter Yiannacouras, The Microarchitecture of FPGA-Based Soft Processors, MASc Thesis, University of Toronto, 2005. (pdf)
- Peter Yiannacouras, An Automatic Cache Generator for Stratix FPGAs, BASc Thesis, University of Toronto, 2003. (pdf)
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