Professor in the Department of Electrical and Computer Engineering at the University of Toronto
NSERC/Intel Industrial Research Chair in Programmable Silicon
Faculty Affiliate, Vector Institute for Artificial Intelligence
IEEE Fellow, Fellow of the National Academy of Inventors
- Architecture changes to make spatially programmable hardware (FPGAs) more efficient and easier to use. A major focus in this area is creating new FPGA architectures that are more efficient for deep learning inference, yet still highly programmable and general purpose enough to implement entire systems. Another focus is creating FPGAs that are more datacenter-friendly, allowing easier design and simpler use by multiple applications through techniques like embedding NoCs in the fabric.
- New Computer-Aided Design tools to make it easier to design hardware, and to investigate new FPGA architectures.
- Methods to map deep learning applications to direct hardware execution on programmable devices like FPGAs. By generating customized hardware for each layer in a neural network we can outperform prior approaches, and by changing the chips themselves in our FPGA architecture research we can improve efficiency even more.
- CAD tools to make FPGAs easier to debug and better suited to the data center; in particular we are seeking ways to let FPGA tasked be interrupted and safely context switched in and out of hardware in a data center.
- Hardware acceleration of important problems and software tools to optimize medical treatments; most recently I've focused on simulating photon scattering in complex human tissue to aid photodynamic cancer treatments. This is a form of light-activated chemotherapy which can better target tumours than conventional chemotherapy, but which requires advanced computation to determine where the fiber optic light probes should be placed (via hyperdermic needles) to achieve the best results.
Links to learn more
- I am a member of the
Intel/Vmware Crossroads 3D FPGA Academic Research Centre
. In collaboration with researchers at Carnegie Mellon University, the University of Texas at Austin and Intel and Vmware, we are working to develop the next-gneration of FPGA architectures, CAD tools and accelerators.
- I am a leader of the Verilog-to-Routing (VTR) project that is developiong open-source CAD tools for FPGA research and to enable novel FPGAs.
- You can see more of my views on research and areas of interest in this researcher spotlight interview of me by Rajsaktish Sankaranarayanan of SIGDA and Intel.
Biography and CV
LinkedIn profile and News
Research and Design Students
Service and Committees
Software and benchmarks, including VPR, the Titan23 benchmarks, COFFE, and EasyGL
Entrepreneurship mentoring and activities
Our very sincere thanks to the companies and organizations that have sponsored our research, which include:
The Natural Sciences and Engineering Research Council of Canada (NSERC), Intel, Altera, Google, Huawei, IBM, Lattice Semiconductor, The Canadian Foundation for Innovation (CFI), the Ontario Centres of Excellence (OCE), the Ontario Research Fund (ORF), the Semiconductor Research Corporation, The Southern Ontario Smart Computing Innovation Program (SOSCIP), Toshiba Corporation, Texas Instruments, and Theralase
I am very honoured that our paper VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling has won the ACM TRETS Best Paper of 2021 Award. Thanks to all who contributed to this major set of enhancements and improvements to the Verilog to Routing infrastructure!
Check out the FPGA Architecture: Principles and Progression
survey paper by Andrew Boutros and I in IEEE Circuits and Systems magazine. Our goal was to synthesize key academic research results and principles with the latest industrial FPGA architecture innovations for each aspect of FPGAs; hope you enjoy it!
I am very grateful to have been named a Fellow of the National Academy of Inventors. See more details
I presented an hour long invited talk on the VTR (open-source CAD for FPGA architecture exploration) at the VLSI SoC 2020 Conference. You can see the slides here or see the publications link for more formats.
Adrian Ludwin, Ketan Padalia and myself were honoured to have our paper on parallel placement inducted into the FPGA Hall of Fame. I gave an invited talk on this work, and my personal history in parallel CAD and thoughts for the future at FPL. See the recording (starting at 54 min in) or check out the slides.
I am grateful to the IEEE for elevating me to IEEE Fellow.
For my thoughts and a personal history of FPGA research, please see the SIGDA researcher spotlight interview of me by Rajsaktish Sankaranarayanan.
Congratulations to Andrew Boutros and Sadegh Yazdanshenas for receiving the Best Paper Award at the 2018 Field Programmable Logic and Applications Conference for their paper "Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs."
Congratulations to Kosuke Tatsumura and Sadegh Yazdanshenas for their paper on improving FPGAs with magnetic tunnel junctions which won the best paper award at the 2016 IEEE Int. Conference on Field Programmable Technology. Their paper showed that integrating magnetic tunnel junctions in an FPGA enables 3x the block RAM memory capacity, with no die size increase.
I was recently honoured to receive the Ontario Professional Engineers Medal for Engineering Excellence. [Video on my career and research]
Our work on using FPGAs (agile computing) to make an emerging form of minimally invasive cancer treatment (photodynamic therapy) more effective and usable in more situations was featured at the recent IBM CASCON.
I presented a keynote on The Case for Embedding Networks-on-Chip in FPGA Architectures at the recent Field Programmable Technology Conference in New Zealand.
I recently received the FPL Community Award for my contributions to placement and routing frameworks for FPGA research. I have had many students and collaborators on the VPR and VTR projects that form this framework; my thanks to them all and they should share in this recognition.
Two of the group's papers were recently selected as being amongst a select group of influential papers from the first 25 years of the Field Programmable Logic and Applications Conference, the FPL 25.
Congratulations to Kevin Murray for winning the prestigious NSERC Canada Graduate Scholarship! Kevin is working on new CAD tools for FPGAs that can divide-and-conquer the implementation of an FPGA design to keep runtime and design time reasonable despite ever growing chip sizes.
Congratulations to Mohamed Abdelfattah and Andrew Bitar on their FPGA 2015 paper Take the Highway: Design for Embedded NoCs on FPGAs won the Best Paper Award! This paper defined design rules for using an embedded NoC on an FPGA in both latency-sensitive and latency-insensitive design styles, and showed that such a NoC can reduce FPGA wiring congestion and enable new applications like high-bandwidth Ethernet switching.
Congratulations to Matthew An on his FCCM 2014 paper Speeding Up FPGA Placement: Parallel Algorithms and Methods won the Best Paper Award! This paper showed a new method to speed up placement using multiple processors that achieves a 34x time reduction on 64 processors, with only a 2% quality loss vs. high-quality sequential placement.
Congratulations to Team FuelWear of the Entrepreneurship Hatchery at the University of Toronto. I was Team FuelWear's faculty mentor, and the team created a successful Indiegogo campaign and won the Lacavera Prize, raising over $100,000 in total for their business idea of smart, electrically-heated winter sportwear.
Congratulations to Mohamed Abdelfattah, whose FPL 2013 paper The Power of Communication: Energy Efficient NoCs for FPGAs won the S. Vassiliadis Award for Best Paper. This paper shows that NoCs on FPGAs can be made surprisingly power-efficient, approaching the power-efficiency of even the lowest-level FPGA communication styles.
Congratulations to Jeff Cassidy on being awarded the prestigious Canadian Institute of Health Research Canada Graduate Scholarship to pursue his PhD! Jeff will be building on his MASc work to use hardware to rapidly compute optimized photodynamic cancer treatment plans, as he works toward a clinical cancer treatment system.
Award ceremony picture
Congratulations to Mohamed Abdelfattah on being awarded a Vanier Canada Graduate Scholarship (Canada's highest award for graduate students)!
Award ceremony picture
I hold the NSERC/Altera Industrial Research Chair in Programmable Silicon; my sincere thanks to NSERC and Altera for this great research opportunity.
A panel of experts has chosen the FPGA 20: the twenty-five most influential papers from 20 years of the International FPGA Symposium. Six of my papers are included in the FPGA 25.
Read more on the University of Toronto's impact in the FPGA 20 (and the FPGA industry) here.
I co-chaired the FPGA 2012 workshop, which was on "FPGAs in 2032: Opportunities and Challenges for the Next 20 Years." Seven visionaries from industry and academia shared their thoughts, leading to a very interesting set of presentations and discussion. See the slides and video