Kevin E. Murray


I am a PhD candidate in the Department of Electrical and Computer Engineering at the Univeristy of Toronto. I completed a BASc in Engineering Science at the University of Toronto in 2012, and an MASc in 2014.

I've previously interned at Advanced Micro Devices (AMD) in Sunnyvale California, where I worked on design flows and methodologies for Static Timing Analysis and developed custom floorplan optimization tools. I was also a visiting Research Associate in the Circuits and Systems Group at Imperial College London UK in late 2015, where I worked on methods to reduce pessimism in Static Timing Analsysis for approximate computing.

Research Interests

My current research interests include CAD algorithms and design methodologies for digital circuits. I'm interested in elastic circuit design techniques, such as latency insensitive design, that relax the synchronous assumption governing conventional digital circuits. In particular, I'm interested in investigating what impact these techniques would have on FPGA CAD tools, and what new avenues for design optimization they enable.


Benchmark, Software and Hardware Releases

Contact Info

Email: k m u r r a y (AT) eecg (DOT) utoronto (DOT) ca [delete spaces and use real @ and .]

Office: D. L. Pratt, Room 372 (PT372)

Mailing Address:
Dept. of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, ON, Canada
M5S 3G4