Kevin E. Murray
I am a PhD candidate in the Department of Electrical and Computer Engineering at the Univeristy of Toronto.
I completed a BASc in Engineering Science at the University of Toronto in 2012, and an MASc in 2014.
I've previously interned at Advanced Micro Devices (AMD) in Sunnyvale California, where I worked on
design flows and methodologies for Static Timing Analysis and developed custom floorplan optimization tools.
I was also a visiting Research Associate in the Circuits and Systems Group at Imperial College London UK in late 2015,
where I worked on methods to reduce pessimism in Static Timing Analsysis for approximate computing.
My current research interests include CAD algorithms and design methodologies for digital circuits. I'm interested
in elastic circuit design techniques, such as latency insensitive design, that relax the synchronous assumption
governing conventional digital circuits. In particular, I'm interested in investigating what impact these techniques
would have on FPGA CAD tools, and what new avenues for design optimization they enable.
- K. E. Murray, T. Ansell, K. Rothman, A. Comodi and V. Betz "Symbiflow & VPR: An Open-Source Design Flow for Commercial and Novel FPGAs", IEEE Micro, 2020. (pdf, DOI:10.1109/MM.2020.2998435 )
- K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. ElDafrawy, J.-P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent and V. Betz "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", ACM Trans. Reconfig. Technol. Syst. (TRETS), 2020. (pdf, DOI: 10.1145/3388617)
- K. E. Murray, J. Luu, M. J. P. Walker, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K. B. Kent, J. Anderson, J. Rose and V. Betz, "Optimizing FPGA Logic Block Architectures for Arithmetic", To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2020, 1-14. (pdf, DOI: 10.1109/TVLSI.2020.2965772)
- K. E. Murray, S. Zhong and V. Betz, "AIR: A Fast but Lazy Timing-Driven FPGA Router", IEEE/ACM Asia Pacific Design Automation Conference (ASP-DAC), 2020, 1-7. [Acceptance rate: 34%] (pdf, slides, DOI: 10.1109/ASP-DAC47756.2020.9045175)
- K. E. Murray, and V. Betz, "Adaptive FPGA Placement Optimization via Reinforcement Learning", ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) , 2019, 1-6. (pdf, slides)
- K. E. Murray, and V. Betz, "Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization", IEEE Int. Conf. on Field-Programmable Technology (FPT), 2018, 1-8. [Acceptance rate: 25%] (pdf, slides, DOI: 10.1109/FPT.2018.00026)
- K. E. Murray, A. Suardi, V. Betz, G. Constantinides, "Calculated Risks: Quantifying Timing Error Probability with Extended Static Timing Analysis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018, (pdf, DOI: 10.1109/TCAD.2018.2821563)
- K. E. Murray, A. Suardi, V. Betz, G. Constantinides, "Quantifying Error: Extending Static Timing Analysis with Probabilistic Transitions", Design, Automation & Test in Europe (DATE), 2017, pp. 1486-1491. [Acceptance rate: 24%] (pdf, slides, DOI: 10.23919/DATE.2017.7927226)
- K. E. Murray, and V. Betz, "Hetris: Adaptive Floorplanning for Heterogeneous FPGAs", IEEE Int. Conf. on Field-Programmable Technology (FPT), 2015, 1-8. [Acceptance rate: 22%] (pdf, slides, DOI: 10.1109/FPT.2015.7393136)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD", ACM Trans. Reconfig. Technol. Syst. (TRETS), April 2015, pp. 10:1 - 10:18. (pdf, DOI: 10.1145/2629579)
- K. E. Murray and V. Betz, "Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs", ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2014, 223-232. [Acceptance rate: 18%] (pdf, slides, DOI: 10.1145/2554688.2554786)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Titan: Enabling Large and Complex Benchmarks in Academic CAD", IEEE Int. Conf. on Field-Programmable Logic and Applications (FPL), 2013, 1-8. [Acceptance rate: 23%, Nominated for FPL Community Award] (pdf, slides, DOI: 10.1109/FPL.2013.6645503)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "From Quartus To VPR: Converting HDL to BLIF with the Titan Flow", IEEE Int. Conf. on Field-Programmable Logic and Applications (FPL), 2013, 1-1. [Demo Night Paper] (pdf, poster, DOI: 10.1109/FPL.2013.6645626)
Benchmark, Software and Hardware Releases
Email: k m u r r a y (AT) eecg (DOT) utoronto (DOT) ca [delete spaces and use real @ and .]
Office: D. L. Pratt, Room 372 (PT372)
Dept. of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, ON, Canada