University of Toronto ň Computer Engineering Research Group (EECG)

Selected Conference Papers

  1. R.Berryhill, A.Ivrii, N.Veira, and A.Veneris, ``Learning Support Sets in IC3 and Quip: the Good, the Bad, and the Ugly,'' in Formal Methods in CAD (FMCAD), 2017 (PDF)
  2. R.Berryhill, N.Veira, A.Veneris and Z.Poulos, ``Learning Lemma Support Graphs in Quip and IC3,'' in IEEE Int'l Workshop on Verification and Security, 2017 (PDF)
  3. J.Adler, R.Berryhill and A.Veneris, 'An Extensible Perceptron Framework for Revision RTL Debug Automation,'' in ASPDAC'17 (PDF)
  4. Z.Poulos, R.Berryhill, J.Adler, and A.Veneris, ``On Simulation-based Metrics that Characterize Behavior of RTL Errors,'' in Summer Simulation Multi Conference, 2016 (PDF)
  5. J.Adler, R.Berryhill, and A.Veneris, ``Revision Debug with Non-Linear Version History in Regression Verification,'' in IEEE Int'l Workshop on Verification and Security, 2016 (PDF)
  6. R.Berryhill and A.Veneris, ``Efficient Selection of Suspect Sets in Unreachable State Diagnosis,'' in Int'l Symposium on Artificial Intelligence and Mathematics (ISAIM), 2016 (PDF)
  7. J.Adler, D.Maksimovic, and A.Veneris, ``Root-Cause Analysis for Memory-Locked Errors,'' in IEEE/ACM Design and Test in Europe (DATE), 2016 (PDF)
  8. R.Berryhill and A.Veneris, ``A Complete Approach to Unreachable State Diagnosability via Property Directed Reachability,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2016 (PDF)
  9. L.V.Nguyen, D.Maksimovic, T.T.Johnson, and A.Veneris, ``Quantified Bounded Model Checking for Rectangular Hybrid Automata,'' in IEEE Constraints in Formal Verification (CFV) Workshop, 2015 (PDF)
  10. R.Berryhill and A.Veneris, ``Diagnosing Unreachable States Using Property Directed Reachability,'' in IEEE Constraints in Formal Verification (CFV) Workshop, 2015 (PDF)
  11. D. Maksimovic, A.Veneris and Z. Poulos, ``Clustering-based Revision Debug in Regression Verification,'' in IEEE Int'l Conference on Computer Design 2015 (ICCD), (PDF)
  12. Z.Poulos and A.Veneris, ``Mining Simulation Metrics for Failure Triage in Regression Testing,'' in IEEE Int'l On-Line Test Symposium (IOLTS) 2015 (PDF)
  13. B.Le, D. Maksimovic, D.Sengupta, E.Ergin, R.Berryhill and A.Veneris, ``Constructing Stability-based Clock Gating with Hierarchical Clustering,'' in IEEE Int'l Workshop on Power and Timing Modeling, Optimization and Simulation 2015 (PDF)
  14. Z.Poulos and A.Veneris, ``Exemplar-based Failure Triage for Regression Design Debugging,'' in IEEE Latin American Test Symposium, 2015 (PDF)
  15. R. Berryhill and A.Veneris, ``Automated Rectification Methodologies to Functional State-Space Unreachability,'' in IEEE/ACM Design and Test in Europe Conference, 2015 (PDF)
  16. D. Maksimovic, B. Le and A. Veneris, ``Multiple Clock Domain Synchronization in a QBF-based Verification Environment,'' in IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), 2014 (PDF)
  17. Z. Poulos and A. Veneris, ``Clustering-based Failure Triage for RTL Regression Debugging,'' in IEEE Int'l Test Conference (ITC) (PDF)
  18. Z.Poulos, Y.-S.Yang, A.Veneris and B.Le, ``Simulation and Satisfiability Guided Counter-example Triage for RTL Design Debugging,'' in IEEE Int'l Symposium on Quality of Electronic Design (ISQED) 2014, (PDF)
  19. B.Keng, E.Qin, A.Veneris and D.Maksimovic, ``Debugging Missing Assumptionsin a Formal Verification Environment,'' in IEEE Constraints in Formal Verification Workshop (CFV), 2013 (PDF)
  20. B.Keng, E.Qin, A.Veneris and B.Le, ``Automated Debugging of Missing Assumptions,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2014 (PDF)
  21. D.Sengupta, E.Ergin and A.Veneris, ``Early Detection of Current Hot Spots in Power Gated Designs,'' in IEEE Int'l Symposium on Low Power Electronics and Design (ISLPED), 2013 (PDF)
  22. Z.Poulos, Y-.S.Yang and A.Veneris, ``A Failure Triage Engine Based on Error Trace Signature Extraction,'' in IEEE Int'l On-Line Test Symposium, 2013 (PDF)
  23. B.Le, D.Sengupta and A.Veneris, ``Accelerating Post Silicon Debug of Deep Electrical Faults,'' in IEEE Int'l On-Line Test Symposium, 2013 (PDF)
  24. B.Le, D.Sengupta and A.Veneris, ``Reviving Erroneous Stability-based Clock Gating using Partial Max-SAT,'', in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2013 (PDF)
  25. B.Keng and A.Veneris, ``Automated Debugging of Missing Input Constraints in a Formal Verification Environment,'' in Formal Methods in CAD (FMCAD), 2012 (PDF)
  26. B.Keng and A.Veneris, ``Path Directed Abstraction and Refinement in SAT-based Design Debugging,'' in IEEE/ACM Design Automation Conference (DAC), 2012 (PDF)
  27. D.Sengupta, F.M.de Paula, A.J.Hu, A.Veneris and A. Ivanov, ``Lazy Suspect-Set Computation: Fault Diagnosis for Deep Electrical Bugs,'' in IEEE Great Lakes VLSI Symposium, 2012 (PDF)
  28. B.Le, H.Mangassarian and A.Veneris, ``Non-Solution Implications using Reverse Domination in a Modern SAT-based Debugging Environent,'' in IEEE/ACM Design and Test in Europe (DATE) 2012, (PDF)
  29. Z.Poulos, Y-S Yang, J. Anderson and A.Veneris, ``Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug,'' in IEEE/ACM Design and Test in Europe (DATE) 2012, (PDF)
  30. B.Le, H.Mangassarian, B.Keng, and A.Veneris, ``Propelling SAT-based Debugging Using Reverse Domination,'' in IEEE Int'l Workshop on Constraints in Formal Verification, 2011 (PDF)
  31. H.Mangassarian, H.Yoshida, A.Veneris, S.Yamashita and M.Fujita, ``On Error Tolerance and Engineering Change with Partially Programmable Circuits,'' in IEEE/ACM Asian-South Pacific DAC 2012 (ASPDAC), (PDF)
  32. Y.S.Yang, A.Veneris, N.Nicolici and M.Fujita, ``Automated Data Analysis Techniques for a Modern Silicon Debug Environment,'' in IEEE/ACM Asian-South Pacific DAC 2012 (ASPDAC, invited paper), (PDF)
  33. B.Keng, D.E.Smith and A.Veneris, ``Efficient Debugging of Multiple Design Errors,'' in IEEE Microprocessor Test and Verification Workshop, 2011 (PDF)
  34. H.Mangassarian, A.Veneris, D.E.Smith, and S.Safarpour ``Debugging with Dominance: On-the-fly Debug Solution Implications,'' in IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), 2011 (PDF)
  35. D.Sengupta, A.Veneris, S.Wilton, A.Ivanov, R.Saleh, ``Sequence Pair Based Voltage Island Floorplanning,'' in IEEE International Green Computing Conference, 2011 (PDF)
  36. A.Veneris, B.Keng and S.Safarpour, ``From RTL to Silicon: The Case for Automated Debug,'' in IEEE/ACM Asian-South Pacific Design Automation Conference, 2011 (PDF) (invited paper)
  37. B.Keng, S.Safarpour and A.Veneris ``Automated Debugging of SystemVerilog Assertions,'' in IEEE/ACM Design and Test in Europe, 2011 (PDF)
  38. B.Keng and A.Veneris, ``Managing Complexity in Design Debugging with Sequential Abstraction and Refinement,'' in IEEE/ACM Asian-South Pacific Design Automation Conference, 2011 (PDF)
  39. Y.-S.Yang, B. Keng, A.Veneris, N. Nicolici and H. Mangassarian, ``Software Solutions to Automating Data Analysis and Acquisition Setup in Silicon Debug,'' in IEEE Silicon Debug and Diagnosis Workshop, 2010
  40. B.Keng, S.Safarpour and A.Veneris, ``An Automated Framework for Correction and Debug of PSL Assertions,'' in IEEE Microprocessor Verification and Test Workshop, 2010 (PDF)
  41. H. Mangassarian, B.Le, A.Goultiaeva, A.Veneris and F.Bacchus, ``Leveraging Dominators for Preprocessing QBF,'' in IEEE/ACM Design and Test in Europe (DATE), 2010 (PDF)
  42. Y.-S.Yang, B.Keng, N.Nicolici, A.Veneris and S.Safarpour, ``Automated Silicon Debug Data Analysis Techniques for a Hardware Data Acquisition Environment,'' in IEEE Int'l Symposium on Quality of Electronic Design, 2010.
  43. S.Safarpour, A.Veneris and F.Najm, ``Managing Verification Error Traces with Bounded Model Debugging,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2010 (PDF)
  44. S.Safarpour and A.Veneris, ``Automated Debugging with High Level Abstraction and Refinement,'' in IEEE High Level Design Validation and Test Workshop, 2009
  45. B.Keng and A.Veneris, ``Scaling VLSI Design Debugging with Interpolation,'' in Formal Methods in CAD (FMCAD), 2009 (PDF)
  46. Y.Chen, S.Safarpour and A.Veneris, ``Optimal Trace Compaction with Property Preservation,'' in IEEE Midwest Symposium on Circuits and Systems, 2009 (PDF)
  47. A.Veneris and S. Safarpour, ``The Day Sherlock Holmes Decided to do EDA,'' invited talk in IEEE/ACM Design Automation Conference (DAC), 2009 (PDF)
  48. E.Safi, A.Moshovos and A.Veneris, ``A Physical-Level Study of the Compacted Matrix Instruction Scheduler for Duynamically Scheduled Superscalar Processors,'' in IEEE Int'l Symposium on Systems, Architectures, Modeling and Simulation, (PDF)
  49. Y.Chen, S.Safarpour, A.Veneris and J.M.Silva, ``Spatial and Temporal Design Debug using Partial MaxSAT,'' in IEEE Great Lakes VLSI Symposium, 2009 (PDF)
  50. Y.S.Yang, S.Sinha, A.Veneris, R.K.Brayton and D.Smith, ``Sequential Logic Rectifications with Approximate SPFDs,'' in IEEE/ACM Design and Test in Europe (DATE), 2009 (PDF)
  51. Y.S.Yang, N.Nicolici, and A.Veneris ``Automated Data Analysis Solutions to Silicon Debug,'' in IEEE/ACM Design and Test in Europe (DATE), 2009 (PDF)
  52. B.Keng, H.Mangassarian and A.Veneris, ``A Succint Memory Model for Automated Design Debugging,'' in IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), 2008 (PDF)
  53. S.Almukhaizim, Y.Makris, Y.-S.Yang and A.Veneris, ``On the Minimization of Potential Transient Errors and SET in Logic Circuits using SPFD,'' in IEEE Int'l On Line Test Symposium, 2008 (PDF)
  54. S.Safarpour, M.Liffton, H.Mangassarian, A.Veneris and K.A.Sakallah, ``Improved Design Debugging Using Maximum Satisfiability,'' in Formal Methods in CAD (FMCAD) 2007, (PDF)
  55. H.Mangassarian, A.Veneris, S.Safarpour, M.Benedetti and D.Smith, ``A Performance-Driven QBF-Based Iterative Logic Array Representation with Applications to Verification, Debug and Test,'' in Int'l Conference on Computer-Aided Design (ICCAD), 2007, (PDF)
  56. E.Safi, P.Akl, A.Moshovos, A.Veneris and A.Arapoyianni, ``On the Latency, Energy and Area of Checkpointed, Supescalar Register Alias Tables,'' in IEEE Int'l Symposium on Low Power Electronic Devices, 2007 (PDF)
  57. H.Mangassarian, A.Veneris and M.Benedetti, ``Fault Diagnosis Using Quantified Boolean Formulas,'' in IEEE Silicon Debug and Diagnosis Workshop (SDD), Freiburg, May 2007, (PDF)
  58. H.Mangassarian, A.Veneris, S.Safarpour, F.N.Najm and M.S.Abadir, ``Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability,'' in IEEE/ACM Design and Test in Europe Conference (DATE), 2007 (PDF)
  59. S.Safarpour and A.Veneris, ``Abstraction and Refinement Techniques in Automated Design Debugging,'' in IEEE/ACM Design and Test in Europe Conference (DATE), 2007 (PDF)
  60. Y.-S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Automating Logic Rectification by Approximate SPFDs,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2007 (PDF)
  61. S.Safarpour, A.Veneris and Hratch Mangassarian, ``Trace Compaction using SAT-based Reachability Analysis,'' in IEEE/ACM Asian-South Pacific Design Automation Conference (ASPDAC), 2007 (PDF)
  62. E.Safi, A.Moshovos and A.Veneris, ``L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture,'' in IEEE Int'l Symposium on Low Power Electronic Devices, 2006 (PDF)
  63. S.Almukhaizim, Y.Makris, Y.-S.Yang and A.Veneris, ``Seamless Integration of SER in Rewiring-Based Design Space Exploration,'' in IEEE Int'l Test Conference (ITC), 2006 (PDF)
  64. S.Safarpour, A.Veneris, G.Baeckler and R.Yuan, ``Efficient SAT-based Boolean Matching for FPGA Technology Mapping,'' in IEEE/ACM Design Automation Conference (DAC), 2006 (PDF)
  65. S.Safarpour, A.Veneris and R.Dreschler, ``Integrating Observability Don't Cares in All-Solution SAT Solvers,'' in IEEE Int'l Symposium on Circuits and Systems, 2006 (PDF)
  66. G.Fey, S.Safarpour, A.Veneris and R.Drechsler, ``On the Relation Between Simulation-based and SAT-based Diagnosis,'' in IEEE/ACM Design and Test in Europe (DATE) Conference, 2006 (PDF)
  67. M.F.Ali, S.Safarpour, A.Veneris, M.S.Abadir and R.Drechsler, ``Post-Verification Debugging of Hierarchical Designs,'' in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2005 (PDF)
  68. J.B.Liu, M.S.Abadir, A.Veneris and S.Safarpour,``Diagnosing Multiple Transition Faults in the Absense of Timing Information,'' in IEEE Great Lakes VLSI Symposium, 2005 (PDF)
  69. S.Safarpour, G.Fey, A.Veneris and R.Drechsler, ``Utilizing Don't Care States in SAT-based Bounded Sequential Problems,'' in IEEE Great Lakes VLSI Symposium, 2005 (PDF)
  70. Y-S.Yang, A.Veneris, P.Thadikaran and S.Venkataraman, ``Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs,'' in IEEE Design and Test in Europe, 2005 (PDF)
  71. M.Fahim Ali, A.Veneris, S.Safarpour, R.Drechsler, A.Smith and M.S.Abadir, ``Debugging Sequential Circuits Using Boolean Satisfiability,'' in IEEE Int'l Conference of Computer-Aided Design, 2004 (PDF) (PS)
  72. J.B.Liu, M.S.Abadir, R.Chang, A.Veneris, ``Monarch: A Platform for Logic Optimization using ATPG/Diagnosis-based Design Rewiring,'' in IEEE Latin-American Test Workshop 2004 (PDF) (PS)
  73. A.Veneris, R.Chang, M.S.Abadir and M.Amiri, ``Fault Equivalence and Diagnostic Test Generation Using ATPG,'' in IEEE Int'l Symposium on Circuits and Systems, 2004 (PDF)
  74. S.Safarpour, A.Veneris, R.Drechsler and J.Lee, ``Managing Don't Cares in Boolean Satisfiability,'' in IEEE Design Automation and Test in Europe (DATE) Conference, 2004 (PDF)
  75. A.Smith, A.Veneris and A.Viglas, ``Design Diagnosis Using Boolean Satisfiability,'' in IEEE Asian-South Pacific Design Automation Conference 2004 (PDF)
  76. Y.S.Yang, J.B.Liu, P.Thadikaran and A.Veneris, ``Extraction Error Diagnosis and Correction in High-Performance Designs,'' in IEEE International Test Conference 2003 (PDF)
  77. A.Veneris, ``Fault Diagnosis and Logic Debugging Using Boolean Satisfiability,'' in IEEE Microprocessor Test and Verification Workshop, 2003 (PDF)
  78. R.Chang, S.Seyedi, A.Veneris and M.S.Abadir, ``Exact Functional Fault Collapsing in Combinational Logic Circuits,'' in IEEE Latin American Test Workshop 2003, (PDF)
  79. A.Veneris, A.Smith and M.S.Abadir, ``Logic Verification based on Diagnosis Techniques,'' in IEEE Asian-South-Pacific (ASP) Design Automation Conference 2003, (PDF)
  80. J.B.Liu, A.Veneris and H.Takahashi, ``Incremental Diagnosis of Multiple Open Interconnects,'' in IEEE Int'l Test Conference 2002 (PDF)
  81. A.Veneris, M.Abadir and M.Amiri, ``Design Rewiring Using ATPG,'' in IEEE Int'l Test Conference 2002 (PDF)
  82. A.Veneris, M.Amiri and I.Ting, ``Design Rewiring for Power Minimization,'' in ISCAS 2002 (PS)
  83. B.Liu, A.Veneris and M.S.Abadir, ``Efficient and Exact Diagnosis of Multiple Stuck-at Faults,'' 3rd IEEE Latin-American Test Workshop 2002 (PS)
  84. A.Veneris, B.Liu, M.Amiri and M.S.Abadir, ``Incremental Diagnosis and Debugging of Multiple Faults and Errors,'' IEEE Design, Automation and Test in Europe (DATE) Conference, 2002 (PDF)
  85. I.Ting, A.Veneris, and M.S.Abadir, ``ATPG Driven Logic Synthesis for Area and Power Minimization'', 2nd IEEE Latin-American Test Workshop 2001 (postcript)
  86. A.Veneris, M.S.Abadir, and I.Ting, `` Design Rewiring based on Diagnosis Techniques'', IEEE Asian-South-Pacific (ASP) Design Automation Conference, pp 479-481, 2001. Recipient of ASP-DAC 2001's best paper award. (postcript)
  87. A.Veneris, M.S.Abadir, and I.N.Hajj, `` Design Optimization based on Diagnosis Techniques'', 1st IEEE Latin-American Test Workshop 2000 (postcript)
  88. A. Veneris, S. Venkataraman, I. N. Hajj, and W. K. Fuchs,``Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits'', in Proceedings of IEEE VLSI Test Symposium, pp. 58ˇ63, 1999. (posctript)
  89. A. Veneris and I. N. Hajj, ``A Hybrid Approach to Design Error Detection and Correction'', in Proceedings of International Conference on Electronics, Circuits and Systems, 1999. (postcript)
  90. A. Veneris and I. N. Hajj, ``Correcting Multiple Design Errors in Digital VLSI Circuits'', in Proceedings of IEEE International Symposium on Circuits and Systems, 1999. (postcript)
  91. A. Veneris and I. N. Hajj, ``A Fast Algorithm for Locating and Correcting Simple Design Errors'' in Proceedings of 7th IEEE Great Lakes Symposium on VLSI, pp. 45--50, 1997. (postcript)
  92. A. Veneris and I. N. Hajj, ``Error Diagnosis and Correction in VLSI Digital Circuits'', in Proceedings of IEEE Midwest Symposium on Circuits and Systems, pp. 1005--1008, 1997. (postcript)
  93. L. M. Kirousis and A. Veneris, ``Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations'', in 7th International Workshop of Distributed Algorithms, Lecture Notes in Computer Science 725, Springer-Verlag, pp. 54--68, 1993. (postcript)
  94. L. M. Kirousis, P. Tsigas and A. Veneris, ``An Atomicity Criterion for Composite Registers'', in Proceedings of IMACS/IFAC International Symposium on Parallel and Distributed Computing in Engineering Systems (NorthˇHolland), pp. 31ˇ34, 1991. (postcript)

Refereed Journal Papers

  1. R.Berryhill and A.Veneris, ``Methodologies for Diagnosis of Unreachable States via Property Directed Reachability,'' in IEEE Transactions in Computer-Aided Design, 2017 (PDF)
  2. J.Adler and A.Veneris, ``Leveraging Software Configuration Management in Automated RTL Design Debugging,'' in IEEE Design & Test, vol. 34, no.5, pp. 47-53, 2017 (PDF)
  3. Z.Poulos and A.Veneris, ``Exemplar-based Failure Triage for Regression Design Debugging,'' in Journal of Electronic Testing, Theory and Applications (JETTA), 2016 (PDF)
  4. H.Mangassarian, B.Le and A.Veneris, ``Debugging RTL using Structural Dominance,'' in IEEE Trans. on TCAD (PDF)
  5. B.Keng, and A.Veneris, ``Path Directed Abstraction and Refinement in SAT-based Design Debugging,'' in IEEE Trans. on TCAD (PDF)
  6. H.Mangassarian, A.Veneris and F.N.Najm, ``Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability,'' in IEEE Trans. on TCAD (PDF)
  7. Y.S.Yang, A.Veneris and N.Nicolici, ``Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment,'' in IEEE Trans. on VLSI (PDF)
  8. Y.S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Automating Logic Transformations with Approximate SPFDs,'' in IEEE Trans. on Computer-Aided Design (PDF)
  9. E.Safi, A.Moshovos and A.Veneris, ``Two-stage Pipelined Register Renaming,'' in IEEE Trans. on VLSI (PDF)
  10. B.Keng, S.Safarpour and A.Veneris, ``Bounded Model Debugging,'' in IEEE Trans. on CAD (PDF)
  11. Y.Chen, S.Safarpour, J.M.Silva and A.Veneris, ``Automated Design Debugging with Maximum Satisfiability,'' in IEEE Trans. on CAD (PDF)
  12. H.Mangassarian, A.Veneris and M.Benedetti, ``Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug and Test,'' in IEEE Trans. on Computers (PDF)
  13. S.Safarpour and A.Veneris, ``Automated Design Debugging with Abstraction and Refinement,'' in IEEE Trans. on CAD, Oct. 2009 (PDF)
  14. E.Safi, A.Moshovos and A.Veneris, ``On the Latency and Energy of Checkpointed, Superscalar Register Alias Tables,'' in IEEE Trans. on VLSI (PDF)
  15. S.Safarpour, A.Veneris, and R.Drechsler, ``Improved SAT-based Reachability Analysis with Observability Don't Cares,'' in Journal on Satisfiability, Boolean Modeling and Computation, Volume 5 (2008), pages 1-25 (PDF)
  16. E.Safi, A.Moshovos and A.Veneris, ``L-CBF: A Low-Power Fast Counting Bloom Filter Architecture,'' in IEEE Trans. on VLSI (PDF)
  17. Y.-S.Yang, A.Veneris, P.Thadikaran and S.Venkataraman, ``Extraction Error Modeling and Automated Model Debugging in High-Performance Custom Designs,'' in IEEE Trans. on VLSI, July 2006 (PDF)
  18. A.Smith, A.Veneris, M.F.Ali and A.Viglas, ``Fault Diagnosis and Logic Debugging Using Boolean Satisfiability,'' in IEEE Transactions in Computer-Aided Design (PDF)
  19. J.B.Liu and A.Veneris, ``Incremental Fault Diagnosis,'' in IEEE Transactions in Computer-Aided Design (PDF)
  20. A.Veneris and J.B.Liu, ``Incremental Design Debugging in a Logic Synthesis Environment,'' in Springer-Verlag Journal of Electronic Testing: Theory and Applications, vo.21, no.5, pp.485-494, Oct 2005 (PDF)
  21. A.Veneris, ``Logic Rewiring for Delay and Power Minimization,'' in Journal of Information Science and Engineering (PDF)
  22. A.Veneris, R.Chang, M.S.Abadir and S.Seyedi, ``Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG,'' in Journal of Electronic Testing: Theory and Applications (Kluwer), vo.21, no.5, pp.495-502, Oct 2005 (PDF)
  23. A.Veneris and M.S.Abadir, ``Design Rewiring Using ATPG'', IEEE Transactions on Computer-Aided Design, vol. 21, no. 12, pp. 1469-1479, December 2002 (PDF)
  24. A. Veneris and I. N. Hajj, ``Design Error Diagnosis and Correction Via Test Vector Simulation'', in IEEE Transactions on ComputerˇAided Design, vol.18, no.12, pp.1803-1816, December 1999. (PDF)
  25. L. M. Kirousis and A. Veneris, ``Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations'', in Acta Informatica (Springer-Verlag) 32, pp. 155ˇ170, 1995. (postcript)

Books, Book Chapters and Patents

  1. Y.S.Yang, S.Sinha, A.Veneris and R.K.Brayton, ``Advanced Techniques in Logic Synthesis, Optimizations and Applications'' Springer 2010 (Ed: Sunil P. Khatri and Kanupriya Gulati) (PDF)
  2. S.Safarpour, D.Smith, A.Veneris and A.Baker, ``A Methodology for Automated Debugging with Quantified Satisfiability,'' US/Canadian Patent filed, November 2007
  3. A.Veneris, S.Safarpour, M.F.Ali and H.Mangassarian, ``Method, System and Computer Program for Automated Hardware Design Debugging,'' US/Canadian patent filed, October 2006.
  4. M.S.Abadir and A.Veneris, ``Method and system of data processor design by sensitizing logical difference,'' US Patent 7,003,743, Febr 21, 2006
  5. A. Veneris, and D. Kalles, ``Fortran 77'' (in Greek), Voulgaris Editions,1987 (1st ed.), 1989 (2nd ed.).

  University of Toronto ň Computer Engineering Research Group (EECG)