Publications

Google scholar

Patents

To see a list, go to the US Patent Office search. Perform a Basic Search with Inventor name of Betz and Assignee Name of Altera or Toronto.

Books and Book Chapters

	Architecture and CAD for Deep-Submicron FPGAs, V. Betz, J. Rose, and A. Marquardt, Kluwer Academic Publishers, February 1999. 264 pages. ISBN 0-7923-8460-1 Book description (from the back cover). Amazon review
	A. Boutros and V. Betz, "Field-Programmable Gate Array Architecture," Chapnter in Handbook of Computer Architecture, Springer, 2022, pp. 1 - 47.
	M. Hutton, V. Betz and J. Anderson, "FPGA Synthesis and Physical Design," Chapter 16 in Electronic Design Automation for IC Implementation, Circuit Design and Process Technology, CRC Press, 2016, pp. 373 - 414.
	M. Abdelfattah and V. Betz, "Embedded Networks-on-Chip for FPGAs", Chapter 6 in Reconfigurable Logic: Architecture Tools and Applications, P. Gaillardon Ed., Taylor and Francis, 2015, pp. 149 - 184.
	V. Betz, "Placement for General Purpose FPGAs," Chapter 14, in Reconfigurable Computing, A. DeHon and S. Hauck, Eds., Morgan Kauffman, 2007.
	M. Hutton and V. Betz, "FPGA Synthesis and Physical Design," Volume 1, Chapter 13, in Electronic Design Automation for Integrated Circuits Handbook, L. Scheffer, L. Lavagno, and G. Martin, Eds., Taylor and Francis CRC Press, 2006, pp. 13-1 to 13-32.

Conference Keynotes and Invited Talks

• "Verilog to Routing (VTR): A Flexible Open-Source CAD Flow to Explore and Target Diverse FPGA Architectures," IFIP/IEEE Int. Conf. on VLSI (VLSI SoC), October 2020. [ppt slides] [pdf slides] [Abstract]
• "Parallel CAD for FPGAs: A Personal Retrospective and Thoughts for the Future," Int. Conf. on Field-Programmable Logic and Applications (FPL), Sept. 2020. [ppt slides] [pdf slides] [Abstract]
• "The Case for Embedding Networks-on-Chips in FPGAs," IEEE Int. Conf. on Field Programmable Technology, Queenstown, New Zealand, 2015. [Abstract] [ppt] [pdf]

• "FPGAs at 28 nm: Meeting the Challenge of Modern Systems-on-a-Chip," IEEE International Conference on Field Programmable Logic and Applications, Milan, Italy, 2010. [Abstract] [PDF]

• "FPGA Challenges and Opportunities at 40 nm and Beyond,". IEEE International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, 2009. [Abstract] [PDF]

Conference Panel & Workshop Presentations

• "The Computational Battle for Deep Learning," ACM/SIGDA International Symposium on FPGAs,, Monterey, CA, 2018. Panel Organizer and Moderator. My opening slides
• "FPGAs in 2032: Challenges and Opportunities for the Next 20 Years," ACM/SIGDA International Symposium on FPGAs,, Monterey, CA, 2012. Workshop co-chair. Slides and video.

• "Grand Challenges in FPGA Research," ACM/SIGDA International Symposium on FPGAs,, Monterey, CA, 2007. [PDF]

• "Will Power Kill FPGAs?," ACM/SIGDA International Symposium on FPGAs, Monterey, CA, 2006. [PDF]

Journal and Conference Papers and Articles:

See google scholar link for most up-to-date list

• A. Boutros, S. Mahmoudi, A. Mohaghegh, S. More and V. Betz, "Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices," IEEE Int. Conf. on Field-Programamble Technology (FPT), Dec. 2023, pp. 1 - 11. [PDF]
  
  • Received best paper award.
• A. Boutros and V. Betz, "FPGA Architecture: Principles and Progression" IEEE Circuits and Systems Magazine, Vol. 21, No. 2, May 2021, pp. 4 - 29. [PDF]
  
  • An FPGA architecture survey paper, covering key principles, academic research and commercial practice.
• M. Abdelfattah, A. Bitar and V. Betz, "Design and Applications for Embedded Networks-on-Chip on FPGAs," Accepted to IEEE Trans. on Computers.
• H. Wong, V. Betz and J. Rose, "Microarchitecture and Circuits for a 200 MHz Out-of-Order x86 Soft Processor Memory System," Accepted to ACM Trans. on Reconfig. Technology and Systems.
• K. Murray, A. Suardi, G. Constantinides and V. Betz, "Quantifying Error: Extending Static Timing Analysis with Probabilistic Transitions," Accepted to Design Automation and Test in Europe (DATE), 2017.

• S. Yazdanshenas, K. Tatsumura and V. Betz, "Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration," Accepted to ACM Int. Symposium on FPGAs, 2017.

• S. Zhao, I. Ahmed, V. Betz and O. Trescases, "A Robust Dynamic Voltage Scaling (DVS) Scheme for FPGAs with IR Drop Compensation," Accepted to IEEE Applied Power Electronics Conference, 2017.

• K. Tatsumura, S. Yazdanshenas and V. Betz, "High Density, Low Energy, Magnetic Tunnel Junction Based Block RAMs for Memory-Rich FPGAs," IEEE Int. Conf. on Field Programmable Technology, 2016. (Acceptance rate: 20%) Received Best Paper Award. [PDF]
  • Received best paper award

• M. Abdelfattah and V. Betz, "Lynx: CAD for FPGA-Based Networks-on-Chip," Int. Conf. on Field-Programmable Logic and Applications, pp. 1 - 10, 2016. (Acceptance rate: 21%) [PDF]
  • Nominated for best paper award

• O. Petelin and V. Betz, "The Speed of Diversity: Exploring Complex FPGA Routing Toplogies for the Global Metal Layer," pp. 1 - 10, Int. Conf. on Field-Programmable Logic and Applications, 2016. (Acceptance rate: 21%) [PDF]

• I. Ahmed, S. Zhao, O. Trescases and V. Betz, "Measure Twice and Cut Once: Robust Dynamic Voltage Scaling for FPGAs," Int. Conf. on Field-Programmable Logic and Applications, pp. 1 - 11, 2016. (Acceptance rate: 21%) [PDF]

• E. Nasiri, J. Shaikh, A. Hahn Pereira and V. Betz, "Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs," IEEE Trans. on VLSI, May 2016, pp. 1821 - 1834. [PDF]
• H. Wong, V. Betz and J. Rose, "High-Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors," IEEE Int. Conf. on Field-Configurable Custom Computing Machines 2016, pp. 1 - 8. (acceptance rate: 23%) [PDF]
• S. Zhao, I. Ahmed, C. Lamourex, A. Lotfi, V. Betz and O. Trescases, "A Universal Self-Calibrating Dynamic Voltage and Frequency Scaling (DVFS) Scheme with Thermal Compensation for Energy Savings in FPGAs", IEEE Applied Power Electronics Conference, 2016, pp. 1882 - 1887. (acceptance rate: 25%) [PDF]
  • Received best presentation award
• M. Abdelfattah and V. Betz, "Power Analysis of Embedded NoCs on FPGAs and Comparison to Custom Buses", IEEE Trans. on VLSI, Jan. 2016, pp. 165 - 177. [PDF]

• M. Wainberg and V. Betz, "Robust Optimization of Multiple Timing Constraints", IEEE Trans. On CAD, Dec. 2015, pp. 1942 - 1953. [PDF]

• A. Bitar, M. Abdelfattah, and V. Betz, "Bringing Programmability to the Data Plane: Packet Processing with a NoC-Enhanced FPGA", IEEE Int. Conf. on Field Programmable Technology, 2015, pp. 1 - 8. (acceptance rate: 22%) [PDF]

• K. Murray and V. Betz, "HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs", IEEE Int. Conf. on Field Programmable Technology, 2015, pp. 1 - 8. (acceptance rate: 22%) [PDF]

• O. Petelin and V. Betz, "Wotan: A Tool for Rapid Evaluation of FPGA Architecture Routability Without Benchmarks," Int. Conf. on Field-Programmable Logic and Applications, 2015, pp. 1 - 4. (short paper acceptance rate: 41%) [PDF]
• M. Abdelfattah, A. Bitar and V. Betz, "Take the Highway: Design for Embedded NoCs on FPGAs", ACM Int. Symp. on FPGAs, 2015, pp. 98 - 107. (acceptance rate: 16%) [PDF]
  • Received best paper award
• K. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD", ACM TRETS, April 2015, pp. 10:1 - 10:18. [PDF]
• J. Cassidy, V. Betz and L. Lilge, "Treatment Plan Evaluation for Interstitial Photodynamic Therapy in a Mouse Model by Monte Carlo Simulation with FullMonte", Frontiers in Physics, 3:6, February, 2015. [Open Access Link] [PDF]
• J. Cassidy, V. Betz and L. Lilge, "Monte Carlo Fluence Simulation for Prospective Evaluation of Interstitial Photodynamic Therapy Treatment Plans", Proc. SPIE BiOS, 9308-24, 2015. [PDF]
• R. Rashid, G. Steffan and V. Betz, "Comparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS", IEEE Int. Conf. on Field-Programmable Technology, 2014, pp. 20 - 27. (acceptance rate: 29%) [PDF]
• A. Bitar, J. Cassidy, N. Enright-Jerger and V. Betz, "Efficient and Programmable Ethernet Switching with a NoC-Enhanced FPGA", ACM/IEEE Symp. on Architectures for Networking and Communications Systems, 2014. (acceptance rate: 35%) [PDF]
• M. Abdelfattah and V. Betz, "Networks-on-Chip for FPGAs: Hard, Soft or Mixed?," ACM Trans. on Reconfig. Technology and Systems, August 2014, pp 20.1 - 20.22. [PDF]
• H. Wong, V. Betz and J. Rose, "Quantifying the Gap between FPGA and Custom CMOS to Aid Microarchitectural Design," IEEE Trans. on VLSI, Oct. 2014, pp. 2067 - 2080. [PDF]
• M. An, G. Steffen and V. Betz, "Speeding Up FPGA Placement: Parallel Algorithms and Methods," FCCM, 2014, pp. 178 - 185. (acceptance rate: 16%) [PDF]
  • Received best paper award
• J. Cassidy, L. Lilge and V. Betz, "Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs," FCCM,, 2014, pp. 133 - 140. (acceptance rate: 16%) [PDF]
  • Nominated for best paper award
• J. Luu, C. McCullough, S. Wang, S. Huda, Y. Bo, C. Chiasson, K. Kent, J. Anderson, J. Rose and V. Betz, "On Hard Adders and Carry Chains in FPGAs," FCCM, 2014, pp. 52 - 59. (acceptance rate: 16%) [PDF]
• J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose and V. Betz "VTR 7.0: Next Generation Architecture and CAD System for FPGAs," ACM TRETS, Vol. 7, No. 2, June 2014, pp. 6:1 - 6:30. [PDF]
• M. Abdelfattah and V. Betz, "The Case for Embedded Networks-on-Chip on FPGAs," IEEE Micro, January/February 2014, pp. 80 - 89. [PDF]
• K. Murray and V. Betz, "Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs," ACM Int. Conf. on FPGAs, 2014, pp. 223 - 232. (acceptance rate: 18%) [PDF]
• A. Hahn Pereira and V. Betz, "CAD and Architecture for Interposer-Based Multi-FPGA Systems," ACM Int. Conf. on FPGAs, 2014, pp. 75 - 84. (acceptance rate: 18%) [PDF]
• Charles Chiasson and V. Betz, "COFFE: Fully-Automated Transistor Sizing for FPgAs," IEEE Int. Conf. on Field-Programmable Technology, 2013, pp. 34 - 41. (acceptance rate: 23%) [PDF]
• H. Wong, V. Betz and J. Rose, "Efficient Methods for Out-of-Order Load/Store Execution for High-Performance Soft Processors," IEEE Int. Conf. on Field-Programmable Technology, 2013, pp. 442 - 445. (short paper acceptance rate: 51%) [PDF]
• M. Abdelfattah and V. Betz, "The Power of Communication: Energy-Efficient NoCs for FPGAs," IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, pp. 1 - 8. (acceptance rate: 23%) [PDF]
  • Received S. Vassiliadis Award for best paper
  • Chosen as one of the most significant papers from the first 25 years of FPL

• K. Murray, S. Whitty, J. Luu, S. Liu and V. Betz, "Titan: Enabling Large and Realistic Benchmarks for FPGAs," IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, pp. 1 - 8. (acceptance rate: 23%) [PDF]
  • Nominated for FPL Community Award

• C. Chiasson and V. Betz, "Should FPGAs Abandon the Pass Gate?," IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, pp. 1 - 8. (acceptance rate: 23%) [PDF]

• K. Murray, S. Whitty, J. Luu, S. Liu and V. Betz, "From Quartus to VPR: The Titan CAD Flow," IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013. (demo night paper) [PDF]

• J. Cassidy, L. Lilge and V. Betz, "FullMonte: a Framework for High-Performance Monte Carlo Simulation of Light through Turbid Media with Complex Geometry, Proc. SPIE 8592, Biomedical Applications of Light Scattering VII, Feb. 2013. [PDF]

• M. Abdelfattah and V. Betz, "Augmenting FPGAs with Embedded Networks-on-Chip," Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2013.[PDF]

• M. Abdelfattah and V. Betz, "Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip," IEEE Int. Conf. on Field-Programmable Technology, 2012, pp. 95 - 103. (acceptance rate: 21%) [PDF]

• W. Zhang, V. Betz and J. Rose, "Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver," ACM Trans. on Reconfigurable Technology and Systems, March 2012, pp. 6:1 - 6:26. [PDF]

• V. Betz, "FPGAs, Programming Models and Kit Cars," The Last Byte article, IEEE Design and Test of Computers, July/August 2011, p. 112. [Computing Now Link] [PDF]

• A. Ludwin and V. Betz, "Efficient and Deterministic Parallel Placement for FPGAs," ACM Trans. on Design Automation of Electronic Systems, Vol. 16, No. 3, June 2011, pp. 22:1 - 22:23. [PDF]

• H. Wong, J. Rose and V. Betz, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture," ACM Int. Symp.on FPGAs, 2011, pp. 5 - 14. [PDF]

• S. Brown and V. Betz, "Recent FPGA Advances and Challenges," 10th Int. Conf. on Engineering of Reconfigurable Systems and Algorithms, 2010. [Abstract] [PDF]

• D. Chen, D. Singh, J. Chromczak, D. Lewis, R. Fung, D. Neto and V. Betz, "A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in FPGAs," ACM Int. Symp. on Field Programmable Gate Arrays, 2010, pp. 167 - 176. [Abstract] [PDF]

• W. Zhang, V. Betz and J. Rose, "Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver," IEEE Int. Conf. on Field-Programmable Technology, 2008, pp. 17 - 24. [Abstract] [PDF]

• R. Fung, V. Betz, and W. Chow, "Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations," IEEE Trans. on Computer-Aided Design of Circuits and Systems, April 2008, pp. 686 - 697. [Abstract] [PDF]

• A. Ludwin, V. Betz and K. Padalia, "High-Quality, Deterministic Parallel Placement for FPGAs on Commodity Hardware," ACM / Sigda Int. Symp. on FPGAs, 2008, pp. 14 - 23. [Abstract] [PDF]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• R. Tessier, V. Betz, D. Neto, A. Egier and T. Gopalsamy, "Power-efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks," IEEE Trans. on Computer-Aided Design of Circuits and Systems, Feb. 2007, pp. 278 - 290. [Abstract] [PDF]

• R. Tessier, V. Betz, D. Neto and T. Gopalsamy, "Power-Aware RAM Mapping for FPGA Embedded Memory Blocks," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2006, pp. 189 - 198. [Abstract] [PDF]

• D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff and J. Rose, "The Stratix II Logic and Routing Architecture," ACM/Sigda International Symposium on Field Programmable Gate Arrays, 2005, pp. 14 - 20. [Abstract] [PDF]

• R. Fung, V. Betz and W. Chow, "Simultaneous Short-Path and Long-Path Timing Optimization for FPGAs," IEEE International Conference on Computer-Aided Design, November 2004, 838 - 845. [Abstract] [PDF]

• D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff and J. Rose, ``The Stratix Routing and Logic Architecture,'' ACM/Sigda International Symposium on Field-Programmable Gate Arrays, February 2003, pp. 12 - 20. [Abstract] [PDF]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Speed and Area Tradeoffs in Cluster-Based FPGA Architectures,'' IEEE Transactions on VLSI Systems, February 2000, pp. 84 - 93. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Automatic Generation of FPGA Routing Architectures from High-Level Descriptions,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 175 - 184. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Timing-Driven Placement for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2000, pp. 203 - 213. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• V. Betz and J. Rose, ``Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,'' IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1999, pp. 171 - 174. [Abstract] [PDF] [Gzipped PostScript]

• V. Betz and J. Rose, ``FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density,''ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 59 - 68. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• A. Marquardt, V. Betz and J. Rose, ``Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 37 - 46. [Abstract] [PDF] [Gzipped Postscript]
  • Selected as one of the FPGA 20 (most significant papers in the 20 years of the FPGA Symposium)

• V. Betz and J. Rose, ``Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency,'' IEEE Transactions on VLSI Systems, September 1998, pp. 445 - 456. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``How Much Logic Should Go in an FPGA Logic Block?,'' IEEE Design and Test Magazine, Spring 1998, pp. 10 - 15. [Abstract] [PDF] [Gzipped Postscript]

• J. Swartz, V. Betz and J. Rose, ``A Fast Routability-Driven Router for FPGAs,'' ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, 1998, pp. 140 - 149. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``VPR: A New Packing, Placement and Routing Tool for FPGA Research,'' Seventh International Workshop on Field-Programmable Logic and Applications, London, UK, 1997, pp. 213 - 222. [Abstract] [PDF] [Gzipped Postscript]
  • Chosen as one of the most significant papers from the first 25 years of FPL
  • Received FPL Community Award

• V. Betz and J. Rose, ``Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size,'' IEEE Custom Integrated Circuits Conference, Santa Clara, CA, 1997, pp. 551 - 554. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,'' IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1996, pp. 652 - 659. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and J. Rose, ``Using Architectural Families to Increase FPGA Speed and Density,'' ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, 1995, pp. 10 - 16. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and R. Mittra, ``A Boundary Condition to Absorb Both Propagating and Evanescent Waves in a Finite-Difference Time-Domain Simulation,'' IEEE Microwave and Guided Wave Letters, June 1993, pp. 182 - 184.

• V. Betz and R. Mittra, ``Comparison and Evaluation of Boundary Conditions for the Absorption of Guided Waves in an FDTD Simulation,'' IEEE Microwave and Guided Wave Letters, Dec. 1992, pp. 499 - 501.

• V. Betz, N. P. East and A. Sebak, ``Applications of Planar Near-Field Measurements to Electromagnetic Radiation and Interference Problems,'' Canadian Conference on Electrical and Computer Engineering, Montreal, PQ, 1991, pp. 72.1.1 - 72.1.4.

Tutorials

• V. Betz and S. Verma, "Manage Performance and Power Using 40 nm FPGAs," Internet Seminar, July 2008. [PDF] [video]

• V. Betz and S. Rajput, "Learn to Design with Stratix III FPGAs Programmable Power Technology and Selectable Core Voltage," Internet Seminar, March 2007. [PDF] [video]

• V. Betz, "Using Stratix III FPGAs to Achieve Higher Performance Systems with Lower Power", Internet Seminar, Dec. 2006.

• V. Betz and S. Rajput, "Reduce FPGA Power With Automatic Optimization & Power-Efficient Design", Internet Seminar, Nov. 2005. [PDF]

• V. Betz and P. Ekas, "Power Solutions for Leading-Edge FPGAs", Internet Seminar, March 2005. [PDF]

Theses and Technical Reports:

• V. Betz and J. Rose, ``Architecture and CAD for the Speed and Area Optimization of FPGAs,'' Ph.D. Dissertation University of Toronto, 1998.

• V. Betz and J. Rose, ``On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs,'' CSRI Technical Report #358, Department of Electrical and Computer Engineering, University of Toronto, 1996. [Abstract] [PDF] [Gzipped Postscript]

• V. Betz and R. Mittra, ``Absorbing Boundary Conditions for the Finite-Difference Time-Domain Analysis of Guided-Wave Structures,'' M.S. Thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1993.

• V. Betz, N. P. East, and A. Sebak, ``Calculation of Far-Field Radiation Pattern from Near-Field Antenna Measurements,'' B.Sc. Thesis, Department of Electrical and Computer Engineering, University of Manitoba, 1991.