Farid N. Najm

Publications

Books, journal papers, preprints, and conference papers in computer-aided design for integrated circuits.
IEEE Copyright: IEEE owns the copyright to all IEEE-published material below. Personal use is permitted; any other reuse requires IEEE permission.

Books & Book Chapters

  1. 1 G. K. Yeap and F. N. Najm, Editors, Low Power VLSI Design and Technology. Singapore: World Scientific Publishing Co., 1996 (ISBN: 9-810-22518-0).
  2. 2 E. A. Amerasekera and F. N. Najm, Failure Mechanisms in Semiconductor Devices, 2nd Ed. Chichester: John Wiley & Sons, 1997 (ISBN: 0-471-95482-9).
    Errata
  3. 3 F. N. Najm, "Power Estimation and Optimization," in Encyclopedia of Electrical and Electronics Engineering, Vol. 16, pp. 645–655. New York, NY: John Wiley & Sons, 1999 (ISBN: 0-471-13957-2).
  4. 4 F. N. Najm, Circuit Simulation. Hoboken, NJ: John Wiley & Sons, 2010 (ISBN: 978-0-470-53871-5).
    Publisher Errata

Journal Papers

  1. Reliability and Probabilistic Simulation
  2. 1R. Burch, J. Hall, F. Najm, D. Hocevar, P. Yang, and M. McGraw, "A CAD system for modeling voltage drop and electromigration in VLSI metallization patterns," Texas Instruments Technical Journal, vol. 5, no. 3, pp. 74–84, May–June 1988.
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  3. 2F. Najm, R. Burch, P. Yang, and I. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 9, no. 4, pp. 439–450, April 1990. ★ Best Paper
    Erratapdf
  4. 3F. Najm and I. Hajj, "The complexity of fault detection in MOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 9, no. 8, pp. 995–1001, September 1990.
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  5. 4F. Najm, I. Hajj, and P. Yang, "An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 10, no. 11, pp. 1372–1381, November 1991.
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  6. Gate-Level Power and Activity Estimation
  7. 5F. Najm, "Transition density: a new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 310–323, February 1993.
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  8. 6R. Burch, F. Najm, P. Yang, and T. Trick, "A Monte Carlo approach for power estimation," IEEE Transactions on VLSI Systems, vol. 1, no. 1, pp. 63–71, March 1993.
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  9. 7F. Najm, "Low-pass filter for computing the transition density in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 13, no. 9, pp. 1123–1131, September 1994.
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  10. 8F. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 446–455, Dec. 1994. Invited
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  11. 9H. Kriplani, F. N. Najm, and I. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 14, no. 8, pp. 998–1012, August 1995.
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  12. High-Level and RTL Power Estimation
  13. 10M. Nemani and F. N. Najm, "Towards a high-level power estimation capability," IEEE Transactions on Computer-Aided Design, vol. 15, no. 6, pp. 588–598, June 1996.
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  14. 11F. N. Najm and M. G. Xakellis, "Statistical estimation of the switching activity in VLSI circuits," VLSI Design, vol. 7, no. 3, pp. 243–254, 1998.
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  15. 12R. Panda and F. N. Najm, "Post-mapping transformations for low-power synthesis," VLSI Design, vol. 7, no. 3, pp. 289–301, 1998.
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  16. 13M. Nemani and F. N. Najm, "High-level area and power estimation for VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 18, no. 6, pp. 697–713, June 1999.
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  17. 14S. Gupta and F. N. Najm, "Power modeling for high level power estimation," IEEE Transactions on VLSI Systems, vol. 8, no. 1, pp. 18–29, February 2000.
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  18. 15S. Gupta and F. N. Najm, "Analytical models for RTL power estimation of combinational and sequential circuits," IEEE Transactions on Computer-Aided Design, vol. 19, no. 7, pp. 808–814, July 2000.
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  19. 16J. Kozhaya and F. N. Najm, "Power estimation for large sequential circuits," IEEE Transactions on VLSI Systems, vol. 9, no. 2, pp. 400–407, April 2001.
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  20. Interconnect, Sequential Circuits, and Power Grid — Beginnings
  21. 17S. Bodapati and F. N. Najm, "Pre-layout estimation of individual wire lengths," IEEE Transactions on VLSI Systems, vol. 9, no. 6, pp. 943–958, December 2001.
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  22. 18V. Saxena, F. N. Najm, and I. N. Hajj, "Estimation of state line statistics in sequential circuits," ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 3, pp. 455–473, July 2002.
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  23. 19S. Ramprasad, I. N. Hajj, and F. N. Najm, "A technique for improving dual-output domino logic," IEEE Transactions on VLSI Systems, vol. 10, no. 4, pp. 508–511, August 2002.
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  24. 20J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis," IEEE Transactions on Computer-Aided Design, vol. 21, no. 10, pp. 1148–1160, October 2002.
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  25. 21S. Gupta and F. N. Najm, "Energy and peak-current per-cycle estimation at RTL," IEEE Transactions on VLSI Systems, vol. 11, no. 4, pp. 525–537, August 2003.
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  26. Leakage Power, FPGAs, and Power Grid Analysis
  27. 22N. Azizi, F. N. Najm, and A. Moshovos, "Low-leakage asymmetric-cell SRAM," IEEE Transactions on VLSI Systems, vol. 11, no. 4, pp. 701–715, August 2003.
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  28. 23J. H. Anderson and F. N. Najm, "Power estimation techniques for FPGAs," IEEE Transactions on VLSI Systems, vol. 12, no. 10, pp. 1015–1027, October 2004.
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  29. 24A. Moshovos, B. Falsafi, F. N. Najm, and N. Azizi, "A case for asymmetric-cell cache memories," IEEE Transactions on VLSI Systems, vol. 13, no. 7, pp. 877–881, July 2005.
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  30. 25K. M. Buyuksahin and F. N. Najm, "Early power estimation for VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 24, no. 7, pp. 1076–1088, July 2005.
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  31. 26I. A. Ferzli and F. N. Najm, "Analysis and verification of power grids considering process-induced leakage current variations," IEEE Transactions on Computer-Aided Design, vol. 25, no. 1, pp. 126–143, January 2006.
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  32. 27J. H. Anderson and F. N. Najm, "Active leakage power optimization for FPGAs," IEEE Transactions on Computer-Aided Design, vol. 25, no. 3, pp. 423–437, March 2006.
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  33. 28S. Bodapati and F. N. Najm, "High-level current macro-model for logic blocks," IEEE Transactions on Computer-Aided Design, vol. 25, no. 5, pp. 837–855, May 2006.
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  34. Dynamic Range, Statistical Timing, and Process Variations
  35. 29B. Wu, J. Zhu, and F. N. Najm, "Dynamic range estimation," IEEE Transactions on Computer-Aided Design, vol. 25, no. 9, pp. 1618–1636, September 2006.
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  36. 30D. Kouroussis, R. Ahmadi, and F. N. Najm, "Voltage-aware static timing analysis," IEEE Transactions on Computer-Aided Design, vol. 25, no. 10, pp. 2156–2169, October 2006.
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  37. 31F. N. Najm, N. Menezes, and I. A. Ferzli, "A yield model for integrated circuits and its application to statistical timing analysis," IEEE Transactions on Computer-Aided Design, vol. 26, no. 3, pp. 574–591, March 2007.
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  38. 32N. Azizi, M. M. Khellah, V. De, and F. N. Najm, "Variations-aware low-power design and block clustering with voltage scaling," IEEE Transactions on VLSI Systems, vol. 15, no. 7, pp. 746–757, July 2007.
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  39. 33S. Onaissi and F. N. Najm, "A linear-time approach for static timing analysis covering all process corners," IEEE Transactions on Computer-Aided Design, vol. 27, no. 7, pp. 1291–1304, July 2008.
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  40. 34K. R. Heloue and F. N. Najm, "Early analysis and budgeting of margins and corners using two-sided analytical yield models," IEEE Transactions on Computer-Aided Design, vol. 27, no. 10, pp. 1826–1839, October 2008.
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  41. 35K. R. Heloue, N. Azizi, and F. N. Najm, "Full-chip model for leakage current estimation considering within-die correlation," IEEE Transactions on Computer-Aided Design, vol. 28, no. 6, pp. 847–887, June 2009.
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  42. 36J. H. Anderson and F. N. Najm, "Low-power programmable FPGA routing circuitry," IEEE Transactions on VLSI Systems, vol. 17, no. 8, pp. 1048–1060, August 2009.
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  43. Power Delivery, Vectorless Verification, and Timing
  44. 37I. A. Ferzli, E. Chiprout, and F. N. Najm, "Verification and co-design of the package and die power delivery system using wavelets," IEEE Transactions on Computer-Aided Design, vol. 29, no. 1, pp. 92–102, January 2010.
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  45. 38N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification under an RLC model," IEEE Transactions on Computer-Aided Design, vol. 30, no. 5, pp. 691–703, May 2011.
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  46. 39H. Mangassarian, A. Veneris, and F. N. Najm, "Maximum circuit activity estimation using Boolean satisfiability," IEEE Transactions on Computer-Aided Design, vol. 31, no. 2, pp. 271–284, February 2012.
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  47. 40K. R. Heloue, S. Onaissi, and F. N. Najm, "Efficient block-based parameterized timing analysis covering all potentially critical paths," IEEE Transactions on Computer-Aided Design, vol. 31, no. 4, pp. 472–484, April 2012.
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  48. Power Grid Safety and Electromigration — Early Work
  49. 41S. Chatterjee, M. Fawaz, and F. N. Najm, "Redundancy-aware power grid electromigration checking under workload uncertainties," IEEE Transactions on Computer-Aided Design, vol. 34, no. 9, pp. 1509–1522, September 2015.
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  50. 42M. Avci and F. N. Najm, "Verification of the power and ground grids under general and hierarchical constraints," IEEE Transactions on VLSI Systems, vol. 24, no. 2, pp. 729–742, February 2016.
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  51. 43Z. Moudallal and F. N. Najm, "Generating current budgets to guarantee power grid safety," IEEE Transactions on Computer-Aided Design, vol. 35, no. 11, pp. 1914–1927, November 2016.
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  52. 44M. Fawaz and F. N. Najm, "Fast vectorless RLC grid verification," IEEE Transactions on Computer-Aided Design, vol. 36, no. 3, pp. 489–502, March 2017.
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  53. 45S. Chatterjee, V. Sukharev, and F. N. Najm, "Power grid electromigration checking using physics-based models," IEEE Transactions on Computer-Aided Design, vol. 37, no. 7, pp. 1317–1330, July 2018.
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  54. 46Z. Moudallal and F. N. Najm, "Generating current constraints to guarantee RLC power grid safety," ACM Transactions on Design Automation of Electronic Systems, Vol. 22, No. 4, pp. 66:1–66:39, June 2017.
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  55. 47V. Sukharev and F. N. Najm, "Electromigration check: where the design and reliability methodologies meet," IEEE Transactions on Device and Materials Reliability, Vol. 18, No. 4, pp. 498–507, December 2018.
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  56. 48Z. Moudallal and F. N. Najm, "Power scheduling with active RC power grids," IEEE Transactions on VLSI Systems, Vol. 27, No. 2, pp. 444–457, February 2019.
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  57. Electromigration — Equivalent Circuits, Simulation, and Machine Learning
  58. 49F. N. Najm and V. Sukharev, "Electromigration simulation and design considerations for integrated circuit power grids," Journal of Vacuum Science & Technology B, Vol. 38, No. 6, pp. 063204:1–12, Nov/Dec 2020.
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  59. 50S. Torosyan, A. Kteyan, V. Sukharev, J.-H. Choy, and F. N. Najm, "Novel physics-based tool-prototype for electromigration assessment in commercial-grade power delivery networks," Journal of Vacuum Science & Technology B, Vol. 39, No. 1, pp. 013203:1–6, Jan/Feb 2021.
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  60. 51F. N. Najm, "Equivalent circuits for electromigration," Microelectronics Reliability, Vol. 123, pp. 114200:1–16, Aug. 2021.
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  61. 52V. Sukharev, A. Kteyan, F. N. Najm, Y. H. Yi, C. H. Kim, J.-H. Choy, S. Torosyan, and Y. Zhu, "Experimental validation of a novel methodology for electromigration assessment in on-chip power grids," IEEE Transactions on Computer-Aided Design, Vol. 41, No. 11, pp. 4837–4850, November 2022.
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  62. 53T. Hou, F. N. Najm, N. Wong, and H.-B. Chen, "Novel partitioning-based approach for electromigration assessment with neural networks," IEEE Transactions on Computer-Aided Design, Vol. 44, No. 12, pp. 4714–4724, December 2025.
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Preprints & Magazine Articles

  1. 1F. Najm, "Estimating power dissipation in VLSI circuits," IEEE Circuits and Devices Magazine, vol. 10, no. 4, pp. 11–19, July 1994.
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  2. 2F. Najm and J. Abraham, "Accounting for very deep sub-micron effects in silicon models," EE Times, Jan. 9, 2001.
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  3. 3A. Goyal and F. N. Najm, "Efficient RC power grid verification using node elimination," Tech Design Forum, pp. 32–38, June 2011.
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  4. 4F. N. Najm, "Model order reduction for lumped RC transmission lines," IEEE TechRxiv, October 17, 2020.
    doipreprint

Conference Papers

  1. Reliability, Fault Testing, and Probabilistic Simulation
  2. 1I. Hajj and F. Najm, "Test generation for physical faults in MOS VLSI circuits," IEEE 1987 CompEuro Conference, Hamburg, May 1987.
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  3. 2R. Burch, F. Najm, P. Yang, and D. Hocevar, "Pattern-independent current estimation for reliability analysis of CMOS circuits," 25th ACM/IEEE DAC, Anaheim, CA, pp. 294–299, June 1988.
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  4. 3F. Najm, R. Burch, P. Yang, and I. Hajj, "CREST — a current estimator for CMOS circuits," IEEE ICCAD, Santa Clara, CA, pp. 204–207, November 1988.
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  5. 4F. Najm, I. Hajj, and P. Yang, "Electromigration median time-to-failure based on a stochastic current waveform," IEEE ICCD, Cambridge, MA, pp. 447–450, October 1989.
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  6. 5F. Najm, I. Hajj, and P. Yang, "Computation of bus current variance for reliability estimation of VLSI circuits," IEEE ICCAD, Santa Clara, CA, pp. 202–205, November 1989.
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  7. 6F. Najm and I. Hajj, "Probabilistic simulation of very large scale integrated circuits and systems," 1990 Bilkent International Conference, Ankara, Turkey, July 1990.
  8. Gate-Level Power and Activity Estimation
  9. 7F. Najm, "Transition density, a stochastic measure of activity in digital circuits," 28th ACM/IEEE DAC, San Francisco, CA, pp. 644–649, June 1991.
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  10. 8H. Kriplani, F. Najm, and I. Hajj, "Maximum current estimation in CMOS circuits," 29th ACM/IEEE DAC, Anaheim, CA, pp. 2–7, June 1992.
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  11. 9R. Burch, F. Najm, P. Yang, and T. Trick, "McPOWER: A Monte Carlo approach to power estimation," IEEE/ACM ICCAD, Santa Clara, CA, pp. 90–97, November 1992.
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  12. 10H. Kriplani, F. Najm, and I. Hajj, "Resolving signal correlations for estimating maximum currents in CMOS combinational circuits," 30th ACM/IEEE DAC, Dallas, TX, pp. 384–388, June 1993.
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  13. 11H. Kriplani, F. Najm, and I. Hajj, "Worst case voltage drops in power and ground buses of CMOS VLSI circuits," SRC TECHON'93, Atlanta, GA, pp. 402–404, September 1993.
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  14. 12F. Najm, "Improved estimation of the switching activity for reliability prediction in VLSI circuits," IEEE CICC, San Diego, CA, pp. 429–432, May 1994.
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  15. 13M. Xakellis and F. Najm, "Statistical estimation of the switching activity in digital circuits," 31st ACM/IEEE DAC, San Diego, CA, pp. 728–733, 1994.
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  16. 14H. Kriplani, F. Najm, and I. Hajj, "Improved delay and current models for estimating maximum currents in CMOS VLSI circuits," IEEE ISCAS, vol. 1, pp. 435–438, 1994.
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  17. 15F. N. Najm, "Towards a high-level power estimation capability," IEEE International Symposium on Low Power Design, Dana Point, CA, pp. 87–92, April 1995.
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  18. 16V. P. Dabholkar, S. Chakravarty, F. Najm, and J. Patel, "Cyclic stress tests for full scan circuits," IEEE VLSI Test Symposium, Princeton, NJ, pp. 89–94, April–May 1995.
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  19. 17R. Panda and F. N. Najm, "Technology decomposition for low-power synthesis," IEEE CICC, Santa Clara, CA, pp. 627–630, May 1995.
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  20. 18F. N. Najm and M. Y. Zhang, "Extreme delay sensitivity and the worst-case switching activity in VLSI circuits," ACM/IEEE DAC, San Francisco, CA, pp. 623–627, June 1995.
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  21. 19F. N. Najm, S. Goel, and I. N. Hajj, "Power estimation in sequential circuits," ACM/IEEE DAC, San Francisco, CA, pp. 635–640, June 1995.
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  22. 20F. N. Najm, "Feedback, correlation, and delay concerns in the power estimation of VLSI circuits," ACM/IEEE DAC, San Francisco, CA, pp. 612–617, June 1995. Invited
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  23. 21F. N. Najm, "Power estimation techniques for integrated circuits," IEEE/ACM ICCAD, San Jose, CA, pp. 492–499, 1995. Invited Tutorial
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  24. High-Level and RTL Power Estimation
  25. 22M. Nemani and F. N. Najm, "High-level power estimation and the area complexity of Boolean functions," IEEE ISLPED, Monterey, CA, pp. 329–334, August 1996.
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  26. 23L. E. Amaya, P. T. Krein, and F. N. Najm, "A synthesis environment for power electronics," 5th IEEE Workshop on Computers in Power Electronics, Portland, OR, August 1996.
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  27. 24V. Saxena, F. N. Najm, and I. N. Hajj, "Monte-Carlo approach for power estimation in sequential circuits," European Design & Test Conference, Paris, March 1997.
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  28. 25J. P. Halter and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," IEEE CICC, Santa Clara, CA, pp. 475–478, May 1997.
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  29. 26M. Nemani and F. N. Najm, "High-level area prediction for power estimation," IEEE CICC, Santa Clara, CA, pp. 475–478, May 1997.
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  30. 27S. Gupta and F. N. Najm, "Power macromodeling for high level power estimation," 34th DAC, Anaheim, CA, pp. 365–370, June 1997.
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  31. 28R. Panda and F. N. Najm, "Technology-dependent transformations for low-power synthesis," 34th DAC, Anaheim, CA, pp. 650–655, June 1997.
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  32. 29M. Nemani and F. N. Najm, "High-level area and power estimation for VLSI circuits," IEEE/ACM ICCAD, pp. 114–119, Nov. 1997.
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  33. 30J. N. Kozhaya and F. N. Najm, "Accurate power estimation for large sequential circuits," IEEE/ACM ICCAD, pp. 488–493, Nov. 1997.
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  34. 31M. Nemani and F. N. Najm, "Delay estimation for VLSI circuits from a high-level view," 35th DAC, San Francisco, CA, pp. 591–594, June 1998.
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  35. 32S. Gupta and F. N. Najm, "Analytical model for high level power modeling of combinational and sequential circuits," IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como, Italy, pp. 164–172, March 1999.
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  36. 33S. Gupta and F. N. Najm, "Energy-per-cycle estimation at RTL," IEEE ISLPED, San Diego, CA, pp. 121–126, Aug. 1999.
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  37. 34S. Gupta and F. N. Najm, "Power macro-models for DSP blocks with application to high-level synthesis," IEEE ISLPED, San Diego, CA, pp. 103–105, Aug. 1999.
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  38. 35S. Ramprasad, I. N. Hajj, and F. N. Najm, "An optimization technique for dual-output domino logic," IEEE ISLPED, San Diego, CA, pp. 121–126, Aug. 1999.
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  39. Physical Design, Power Grid, and Leakage — Foundations
  40. 36G. Yoh and F. N. Najm, "A statistical model for electromigration failures," IEEE 1st ISQED, San Jose, CA, pp. 45–50, March 2000.
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  41. 37S. Bodapati and F. N. Najm, "Pre-layout estimation of individual wire lengths," ACM SLIP, San Diego, CA, pp. 93–98, April 2000.
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  42. 38K. M. Buyuksahin and F. N. Najm, "High-level power estimation with interconnect effects," IEEE ISLPED, Italy, pp. 197–202, July 2000.
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  43. 39S. Bodapati and F. N. Najm, "Frequency-domain supply current macro-model," IEEE ISLPED, pp. 295–298, Aug. 2001.
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  44. 40J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "I/O buffer placement methodology for ASICs," 8th IEEE ICECS, Malta, pp. 245–248, Sept. 2001.
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  45. 41M. Shahriari and F. N. Najm, "A gate-level timing model for SOI circuits," 8th IEEE ICECS, Malta, pp. 795–798, Sept. 2001.
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  46. 42J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "Multigrid-like technique for power grid analysis," IEEE/ACM ICCAD, pp. 480–487, Nov. 2001.
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  47. 43N. Azizi, A. Moshovos, and F. N. Najm, "Low-leakage asymmetric-cell SRAM," IEEE ISLPED, Monterey, CA, pp. 48–51, August 2002.
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  48. 44K. M. Buyuksahin and F. N. Najm, "High-level area estimation," IEEE ISLPED, Monterey, CA, pp. 271–274, August 2002.
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  49. 45J. H. Anderson and F. N. Najm, "Power-aware technology mapping for LUT-based FPGAs," IEEE ICFPT, Hong Kong, pp. 211–218, December 2002.
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  50. 46J. H. Anderson and F. N. Najm, "Switching activity analysis and pre-layout activity prediction for FPGAs," ACM/IEEE SLIP, Monterey, CA, pp. 15–21, April 2003.
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  51. 47R. S. Guindi and F. N. Najm, "Design techniques for gate-leakage reduction in CMOS circuits," IEEE ISQED, San Jose, CA, pp. 61–65, March 2003.
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  52. 48I. A. Ferzli and F. N. Najm, "Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations," ACM/IEEE DAC-03, Anaheim, CA, pp. 856–859, June 2003.
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  53. 49D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," ACM/IEEE DAC-03, Anaheim, CA, pp. 99–104, June 2003.
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  54. 50R. S. Guindi, R. C. Kordasiewicz, and F. N. Najm, "Optimization technique for FB/TB assignment in PD-SOI digital CMOS circuits," NEWCAS, Montreal, pp. 157–160, June 2003.
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  55. Power Grid, Statistical Timing, and Dynamic Range
  56. 51R. Ahmadi and F. N. Najm, "Timing analysis in presence of power supply and ground voltage variations," IEEE/ACM ICCAD, San Jose, CA, pp. 176–183, November 2003.
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  57. 52I. A. Ferzli and F. N. Najm, "Statistical verification of power grids considering process-induced leakage current variations," IEEE/ACM ICCAD, San Jose, CA, pp. 770–777, November 2003.
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  58. 53J. H. Anderson and F. N. Najm, "Interconnect capacitance estimation for FPGAs," IEEE/ACM ASP-DAC, Yokohama, Japan, pp. 713–718, January 2004.
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  59. 54J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," ACM/SIGDA FPGA, Monterey, CA, pp. 33–41, February 2004.
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  60. 55N. Azizi and F. N. Najm, "An asymmetric SRAM cell to lower gate leakage," IEEE ISQED, San Jose, CA, pp. 534–539, March 2004.
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  61. 56I. A. Ferzli and F. N. Najm, "Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop," IEEE ICICDT, Austin, TX, pp. 17–24, May 2004. Invited
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  62. 57F. N. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," ACM/IEEE DAC, San Diego, CA, pp. 460–465, June 2004.
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  63. 58B. Wu, J. Zhu, and F. N. Najm, "An analytical approach for dynamic range estimation," ACM/IEEE DAC, San Diego, CA, pp. 472–477, June 2004.
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  64. 59D. Kouroussis, R. Ahmadi, and F. N. Najm, "Worst-case circuit delay taking into account power supply variations," ACM/IEEE DAC, San Diego, CA, pp. 652–657, June 2004.
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  65. 60D. Kouroussis, R. Ahmadi, and F. N. Najm, "A worst-case circuit delay verification technique considering power grid voltage variations," NEWCAS-04, Montreal, pp. 157–160, June 2004.
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  66. 61J. H. Anderson and F. N. Najm, "A novel low-power FPGA routing switch," IEEE CICC, Orlando, FL, pp. 719–722, October 2004.
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  67. 62J. H. Anderson and F. N. Najm, "Low-power programmable routing circuitry for FPGAs," IEEE/ACM ICCAD, San Jose, CA, pp. 602–609, November 2004.
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  68. 63B. Wu, J. Zhu, and F. N. Najm, "Dynamic range estimation for nonlinear systems," IEEE/ACM ICCAD, San Jose, CA, pp. 660–667, November 2004.
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  69. Statistical Timing, Process Variations, Leakage, and FPGAs
  70. 64N. Azizi, M. M. Khellah, V. De, and F. N. Najm, "Variations-aware low-power design with voltage scaling," ACM/IEEE DAC-05, Anaheim, CA, pp. 529–534, June 2005.
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  71. 65F. N. Najm, "On the need for statistical timing analysis," ACM/IEEE DAC-05, Anaheim, CA, pp. 764–765, June 2005.
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  72. 66B. Wu, J. Zhu, and F. N. Najm, "A non-parametric approach for dynamic range estimation of nonlinear systems," ACM/IEEE DAC-05, Anaheim, CA, pp. 841–844, June 2005.
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  73. 67N. Azizi and F. N. Najm, "Compensation for within-die variations in dynamic logic by using body-bias," NEWCAS-05, Quebec City, pp. 167–170, June 2005.
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  74. 68G. Nabaa and F. N. Najm, "Minimization of delay sensitivity to process induced voltage threshold variations," NEWCAS-05, Quebec City, pp. 171–174, June 2005.
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  75. 69K. R. Heloue and F. N. Najm, "Effect of statistical clock skew variations on chip timing yield," NEWCAS-05, Quebec City, pp. 211–214, June 2005.
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  76. 70M. Nizam, F. N. Najm, and A. Devgan, "Power grid voltage integrity verification," ACM/IEEE ISLPED-05, San Diego, CA, pp. 239–244, August 2005.
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  77. 71N. Azizi and F. N. Najm, "Look-up table leakage reductions for FPGAs," IEEE CICC-05, San Jose, CA, pp. 187–190, September 2005.
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  78. 72D. Kouroussis, I. A. Ferzli, and F. N. Najm, "Incremental partitioning-based vectorless power grid verification," IEEE/ACM ICCAD-05, San Jose, CA, pp. 358–364, November 2005.
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  79. 73K. R. Heloue and F. N. Najm, "Statistical timing analysis with two-sided constraints," IEEE/ACM ICCAD-05, San Jose, CA, pp. 829–836, November 2005.
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  80. 74G. Nabaa, N. Azizi, and F. N. Najm, "An adaptive FPGA architecture with process variation compensation and reduced leakage," ACM/IEEE DAC-06, San Francisco, CA, pp. 624–629, July 2006.
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  81. 75N. Azizi and F. N. Najm, "A family of cells to reduce the soft-error-rate in ternary-CAM," ACM/IEEE DAC-06, San Francisco, CA, pp. 779–784, July 2006.
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  82. 76K. Pagiamtzis, N. Azizi, and F. N. Najm, "A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme," IEEE CICC-06, San Jose, CA, pp. 301–304, September 2006.
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  83. Power Grid Verification and Parameterized Timing Analysis
  84. 77N. H. Abdul Ghani and F. N. Najm, "Handling inductance in early power grid verification," IEEE/ACM ICCAD-06, San Jose, CA, pp. 127–134, November 2006.
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  85. 78S. Onaissi and F. N. Najm, "A linear-time approach for static timing analysis covering all process corners," IEEE/ACM ICCAD-06, San Jose, CA, pp. 217–224, November 2006.
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  86. 79H. Mangassarian, A. Veneris, S. Safarpour, F. N. Najm, and M. S. Abadir, "Maximum circuit activity estimation using pseudo-Boolean satisfiability," DATE-07, Nice, France, pp. 1538–1543, April 2007.
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  87. 80N. Azizi and F. N. Najm, "Using keeper control and body bias for fine grained threshold voltage compensation in dynamic logic," 20th Canadian Conference on ECE, Vancouver, pp. 1639–1644, April 2007.
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  88. 81K. R. Heloue and F. N. Najm, "Early statistical timing analysis with unknown within-die correlations," ACM/IEEE TAU-07, Austin, TX, pp. 13–18, February 2007.
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  89. 82K. R. Heloue and F. N. Najm, "Early analysis of timing margins and yield," 20th Canadian Conference on ECE, Vancouver, pp. 1114–1120, April 2007.
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  90. 83K. R. Heloue, N. Azizi, and F. N. Najm, "Modeling and estimation of full-chip leakage current considering within-die correlation," ACM/IEEE DAC-07, San Diego, CA, pp. 93–98, June 2007.
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  91. 84I. A. Ferzli, F. N. Najm, and L. Kruse, "Early power grid verification under circuit current uncertainties," ACM/IEEE ISLPED-07, Portland, OR, pp. 116–121, August 2007.
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  92. 85I. A. Ferzli, F. N. Najm, and L. Kruse, "A geometric approach for early power grid verification using current constraints," ACM/IEEE ICCAD-07, San Jose, CA, pp. 40–47, November 2007.
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  93. 86K. R. Heloue and F. N. Najm, "Parameterized timing analysis with general delay models and arbitrary variation sources," ACM/IEEE TAU-08, Monterey, CA, pp. 14–19, February 2008.
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  94. 87K. R. Heloue and F. N. Najm, "Parameterized timing analysis with general delay models and arbitrary variation sources," ACM/IEEE DAC-08, Anaheim, CA, pp. 403–408, June 2008.
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  95. 88I. A. Ferzli, E. Chiprout, and F. N. Najm, "Verification and co-design of the package and die power delivery system using wavelets," IEEE EPEP, San Jose, CA, pp. 7–10, October 2008.
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  96. 89K. R. Heloue, S. Onaissi, and F. N. Najm, "Efficient block-based parameterized timing analysis covering all potentially critical paths," ACM/IEEE ICCAD-08, San Jose, CA, pp. 173–180, November 2008.
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  97. Power Grid and Timing — Vectorless Verification and Sign-Off
  98. 90K. R. Heloue, C. V. Kashyap, and F. N. Najm, "Quantifying robustness metrics in parameterized static timing analysis," ACM/IEEE TAU-09, Austin, TX, pp. 49–54, February 2009.
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  99. 91N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification using an approximate inverse technique," ACM/IEEE DAC-09, San Francisco, CA, pp. 184–189, July 2009.
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  100. 92S. Onaissi, K. R. Heloue, and F. N. Najm, "Clock skew optimization via wiresizing for timing sign-off covering all process corners," ACM/IEEE DAC-09, San Francisco, CA, pp. 196–201, July 2009.
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  101. 93K. R. Heloue, C. V. Kashyap, and F. N. Najm, "Quantifying robustness metrics in parameterized static timing analysis," ACM/IEEE ICCAD-09, San Jose, CA, pp. 209–216, November 2009.
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  102. 94S. Onaissi, K. R. Heloue, and F. N. Najm, "PSTA-based branch and bound approach to the silicon speedpath isolation problem," ACM/IEEE ICCAD-09, San Jose, CA, pp. 217–224, November 2009.
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  103. 95S. Safarpour, A. Veneris, and F. N. Najm, "Managing verification error traces with bounded model debugging," ASP-DAC, Taipei, Taiwan, pp. 601–606, January 2010.
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  104. 96M. Aydonat and F. N. Najm, "Power grid correction using sensitivity analysis," ACM/IEEE ICCAD-10, San Jose, CA, pp. 808–815, November 2010.
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  105. 97M. Avci and F. N. Najm, "Early P/G grid voltage integrity verification," ACM/IEEE ICCAD-10, San Jose, CA, pp. 816–823, November 2010.
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  106. 98A. Goyal and F. N. Najm, "Efficient RC power grid verification using node elimination," DATE-11, Grenoble, France, pp. 257–260, March 2011.
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  107. 99N. H. Abdul Ghani and F. N. Najm, "Power grid verification using node and branch dominance," ACM/IEEE DAC-2011, San Diego, CA, pp. 682–687, June 2011.
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  108. 100P. Al Haddad and F. N. Najm, "Power grid correction using sensitivity analysis under an RC model," ACM/IEEE DAC-2011, San Diego, CA, pp. 688–693, June 2011.
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  109. 101S. Onaissi, F. Taraporevala, J. Liu, and F. N. Najm, "A fast approach for static timing analysis covering all PVT corners," ACM/IEEE DAC-2011, San Diego, CA, pp. 777–782, June 2011.
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  110. 102Abhishek and F. N. Najm, "Incremental power grid verification," ACM/IEEE DAC-2012, San Francisco, CA, pp. 151–156, June 2012.
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  111. 103F. N. Najm, "Overview of vectorless/early power grid verification," ACM/IEEE ICCAD, San Jose, CA, pp. 670–677, November 2012. Invited
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  112. Power Grid Safety and Electromigration — Early Work
  113. 104S. Chatterjee, M. Fawaz, and F. N. Najm, "Redundancy-aware electromigration checking for mesh power grids," ACM/IEEE ICCAD, San Jose, CA, pp. 540–547, November 2013.
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  114. 105M. Fawaz, S. Chatterjee, and F. N. Najm, "A vectorless framework for power grid electromigration checking," ACM/IEEE ICCAD, San Jose, CA, pp. 553–560, November 2013.
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  115. 106Z. Moudallal and F. N. Najm, "Generating circuit current constraints to guarantee power grid safety," ASP-DAC 2015, Chiba/Tokyo, Japan, pp. 358–365, January 2015.
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  116. 107M. Fawaz and F. N. Najm, "Accurate verification of RC power grids," DATE-16, Dresden, Germany, pp. 814–817, March 2016.
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  117. 108M. Fawaz and F. N. Najm, "Fast simulation-based verification of RC power grids," IEEE CCECE-16, Vancouver, Canada, pp. 1182–1187, May 2016.
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  118. 109Z. Moudallal and F. N. Najm, "Generating voltage drop aware current budgets for RC power grids," IEEE ISCAS-16, Montreal, Canada, pp. 2583–2586, May 2016.
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  119. 110A.-A. Yassine and F. N. Najm, "A fast layer elimination approach for power grid reduction," IEEE/ACM ICCAD-16, Austin, TX, November 2016.
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  120. 111S. Chatterjee, V. Sukharev, and F. N. Najm, "Fast physics-based electromigration checking for on-die power grids," IEEE/ACM ICCAD-16, Austin, TX, November 2016. ★ Best Paper
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  121. Electromigration — Physics-Based and Advanced Methods
  122. 112V. Sukharev, A. Kteyan, J.-H. Choy, S. Chatterjee, and F. N. Najm, "Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids," IEEE IRPS, Monterey, CA, April 2017. Invited
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  123. 113M. Fawaz and F. N. Najm, "Parallel simulation-based verification of RC power grids," IEEE ISVLSI-17, Bochum, Germany, pp. 445–452, July 2017.
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  124. 114J.-H. Choy, V. Sukharev, S. Chatterjee, F. N. Najm, A. Kteyan, and S. Moreau, "Finite-difference methodology for full chip electromigration analysis applied to a 3D IC test structure," IEEE SISPAD-17, Kamakura, Japan, pp. 41–44, September 2017.
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  125. 115Z. Moudallal and F. N. Najm, "Power scheduling with active power grids," IEEE/ACM ICCAD-17, Irvine, CA, pp. 466–473, November 2017.
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  126. 116M. Fawaz and F. N. Najm, "Power grid verification under transient constraints," IEEE/ACM ICCAD-17, Irvine, CA, pp. 593–600, November 2017.
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  127. 117S. Chatterjee, V. Sukharev, and F. N. Najm, "Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems," IEEE/ACM ICCAD-17, Irvine, CA, pp. 659–666, November 2017.
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  128. 118F. N. Najm and V. Sukharev, "Efficient simulation of electromigration damage in large chip power grids using accurate physical models," IEEE IRPS-19, Monterey, CA, March–April 2019. Invited
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  129. 119Z. Moudallal, V. Sukharev, and F. N. Najm, "Power grid fixing for electromigration-induced voltage failures," IEEE/ACM ICCAD-19, Westminster, CO, pp. 1–8, November 2019. ★ Best Paper
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  130. 120A. Issa, V. Sukharev, and F. N. Najm, "Electromigration checking using a stochastic effective current model," IEEE/ACM ICCAD-20, pp. 1–8, November 2020. ★ Best Paper
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  131. 121A. Kteyan, V. Sukharev, A. Volkov, J.-H. Choy, F. N. Najm, Y. H. Yi, C. H. Kim, and S. Moreau, "Electromigration assessment in power grids with account of redundancy and non-uniform temperature distribution," ACM ISPD-23, pp. 124–132, March 2023.
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  132. 122B. Shahriari and F. N. Najm, "Fast electromigration simulation for chip power grids," IEEE ISQED-23, San Francisco, CA, pp. 502–509, April 2023.
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  133. 123C. Feghali and F. N. Najm, "Fast current constraints generation for chip safety," IEEE ISQED-24, San Francisco, CA, pp. 373–380, April 2024.
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