Publications list for Prof. Najm

[Books |Journal Papers |Preprints and Magazine Articles |Conference Papers]

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Books & Book Chapters:

  1. G. K. Yeap and F. N. Najm, Editors, Low Power VLSI Design and Technology. Singapore: World Scientific Publishing Co. 1996 (ISBN: 9-810-22518-0).

  2. E. A. Amerasekera and F. N. Najm, Failure Mechanisms in Semiconductor Devices, 2nd Ed.. Chichester: John Wiley & Sons, 1997 (ISBN: 0-471-95482-9)[Errata].

  3. F. N. Najm, "Power Estimation and Optimization," in Encyclopedia of Electrical and Electronics Engineering, Vol. 16, pp. 645-655. New York, NY: John Wiley & Sons, 1999 (ISBN: 0-471-13957-2).

  4. F. N. Najm, Circuit Simulation, Hoboken, NJ: John Wiley & Sons, 2010 (ISBN: 978-0-470-53871-5). [Errata].

Journal Papers:

  1. R. Burch, J. Hall, F. Najm, D. Hocevar, P. Yang, and M. McGraw, "A CAD system for modeling voltage drop and electromigration in VLSI metallization patterns," Texas Instruments Technical Journal, vol. 5, no. 3, pp. 74-84, May-June 1988. [pdf]

  2. F. Najm, R. Burch, P. Yang, and I. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 9, no. 4, pp. 439-450, April 1990 (Errata in July 1990). (Best Paper Award) [ps] [pdf]

  3. F. Najm and I. Hajj, "The complexity of fault detection in MOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 9, no. 8, pp. 995-1001, September 1990. [ps] [pdf]

  4. F. Najm, I. Hajj, and P. Yang, "An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 10, no. 11, pp. 1372-1381, November 1991. [ps] [pdf]

  5. F. Najm, "Transition density: a new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 310-323, February 1993. [ps] [pdf]

  6. R. Burch, F. Najm, P. Yang, and T. Trick, "A Monte Carlo approach for power estimation," IEEE Transactions on VLSI Systems, vol. 1, no. 1, pp. 63-71, March 1993. [ps] [pdf]

  7. F. Najm, "Low-pass filter for computing the transition density in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 13, no. 9, pp. 1123-1131, September 1994. (and Errata). [ps] [pdf]

  8. F. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Transactions on VLSI Systems, vol. 2, no. 4, pp. 446-455, Dec. 1994. (Invited Paper) [ps] [pdf]

  9. H. Kriplani, F. N. Najm, and I. Hajj, "Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution," IEEE Transactions on Computer-Aided Design, vol. 14, no. 8, pp. 998-1012, August 1995. [ps] [pdf]

  10. M. Nemani and F. N. Najm, "Towards a high-level power estimation capability," IEEE Transactions on Computer-Aided Design, vol. 15, no. 6, pp. 588-598, June 1996. [ps] [pdf]

  11. F. N. Najm and M. G. Xakellis, "Statistical estimation of the switching activity in VLSI circuits," VLSI Design, vol. 7, no. 3, pp. 243-254, 1998. [pdf]

  12. R. Panda and F. N. Najm, "Post-mapping transformations for low-power synthesis," VLSI Design, vol. 7, no. 3, pp. 289-301, 1998. [ps] [pdf]

  13. M. Nemani and F. N. Najm, "High-level area and power estimation for VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 18, no. 6, pp. 697-713, June 1999. [ps] [pdf]

  14. S. Gupta and F. N. Najm, "Power modeling for high level power estimation," IEEE Transactions on VLSI Systems, vol. 8, no. 1, pp. 18-29, February 2000. [ps] [pdf]

  15. S. Gupta and F. N. Najm, "Analytical models for RTL power estimation of combinational and sequential circuits," IEEE Transactions on Computer-Aided Design, vol. 19, no. 7, pp. 808-814, July 2000. [ps] [pdf]

  16. J. Kozhaya and F. N. Najm, "Power estimation for large sequential circuits," IEEE Transactions on VLSI Systems, vol. 9, no. 2, pp. 400-407, April 2001. [ps] [pdf]

  17. S. Bodapati and F. N. Najm, "Pre-layout estimation of individual wire lengths," IEEE Transactions on VLSI Systems, vol. 9, no. 6, pp. 943-958, December 2001. [ps] [pdf]

  18. V. Saxena, F. N. Najm, and I. N. Hajj, "Estimation of state line statistics in sequential circuits," ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 3, pp. 455-473, July 2002. [ps] [pdf]

  19. S. Ramprasad, I. N. Hajj, and F. N. Najm, "A technique for improving dual-output domino logic," IEEE Transactions on VLSI Systems, vol. 10, no. 4, pp. 508-511, August 2002. [ps] [pdf]

  20. J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis," IEEE Transactions on Computer-Aided Design, vol. 21, no. 10, pp. 1148-1160, October 2002. [ps] [pdf]

  21. S. Gupta and F. N. Najm, "Energy and peak-current per-cycle estimation at RTL," IEEE Transactions on VLSI Systems, vol. 11, no. 4, pp. 525-537, August 2003. [ps] [pdf]

  22. N. Azizi, F. N. Najm, and A. Moshovos, "Low-leakage asymmetric-cell SRAM," IEEE Transactions on VLSI Systems, vol. 11, no. 4, pp. 701-715, August 2003. [pdf]

  23. J. H. Anderson and F. N. Najm, "Power estimation techniques for FPGAs," IEEE Transactions on VLSI Systems, vol. 12, no. 10, pp. 1015-1027, October 2004. [pdf]

  24. A. Moshovos, B. Falsafi, F. N. Najm, and N. Azizi, "A case for asymmetric-cell cache memories," IEEE Transactions on VLSI Systems, vol. 13, no. 7, pp. 877-881, July 2005. [pdf]

  25. K. M. Buyuksahin and F. N. Najm, "Early power estimation for VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. 24, no. 7, pp. 1076-1088, July 2005. [pdf]

  26. I. A. Ferzli and F. N. Najm, "Analysis and verification of power grids considering process-induced leakage current variations," IEEE Transactions on Computer-Aided Design, vol. 25, no. 1, pp. 126-143, January 2006. [pdf]

  27. J. H. Anderson and F. N. Najm, "Active leakage power optimization for FPGAs," IEEE Transactions on Computer-Aided Design, vol. 25, no. 3, pp. 423-437, March 2006. [pdf]

  28. S. Bodapati and F. N. Najm, "High-level current macro-model for logic blocks," IEEE Transactions on Computer-Aided Design, vol. 25, no. 5, pp. 837-855, May 2006. [pdf]

  29. B. Wu, J. Zhu, and F. N. Najm, "Dynamic range estimation," IEEE Transactions on Computer-Aided Design, vol. 25, no. 9, pp. 1618-1636, September 2006. [pdf]

  30. D. Kouroussis, R. Ahmadi, and F. N. Najm, "Voltage-aware static timing analysis," IEEE Transactions on Computer-Aided Design, vol. 25, no. 10, pp. 2156-2169, October 2006. [pdf]

  31. F. N. Najm, N. Menezes, and I. A. Ferzli, "A yield model for integrated circuits and its application to statistical timing analysis," IEEE Transactions on Computer-Aided Design, vol. 26, no. 3, pp. 574-591, March 2007. [pdf]

  32. N. Azizi, M. M. Khellah, V. De, and F. N. Najm, "Variations-aware low-power design and block clustering with voltage scaling", IEEE Transactions on VLSI Systems, vol. 15, no. 7, pp. 746-757, July 2007. [pdf]

  33. S. Onaissi and F. N. Najm, "A linear-time approach for static timing analysis covering all process corners," IEEE Transactions on Computer-Aided Design, vol. 27, no. 7, pp. 1291-1304, July 2008. [pdf]

  34. K. R. Heloue and F. N. Najm, "Early analysis and budgeting of margins and corners using two-sided analytical yield models," IEEE Transactions on Computer-Aided Design, vol. 27, no. 10, pp. 1826-1839, October 2008. [pdf]

  35. K. R. Heloue, N. Azizi, and F. N. Najm, "Full-chip model for leakage current estimation considering within-die correlation," IEEE Transactions on Computer-Aided Design, vol. 28, no. 6, pp. 847-887, June 2009. [pdf]

  36. J. H. Anderson and F. N. Najm, "Low-power programmable FPGA routing circuitry," IEEE Transactions on VLSI Systems, vol. 17, no. 8, pp. 1048-1060, August 2009. [pdf]

  37. I. A. Ferzli, E. Chiprout, and F. N. Najm, "Verification and co-design of the package and die power delivery system using wavelets," IEEE Transactions on Computer-Aided Design, vol. 29, no. 1, pp. 92-102, January 2010. [pdf]

  38. N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification under an RLC model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 5, pp. 691-703, May 2011. [pdf]

  39. H. Mangassarian, A. Veneris, and F. N. Najm, "Maximum circuit activity estimation using Boolean satisfiability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 271-284, February 2012. [pdf]

  40. K. R. Heloue, S. Onaissi, and F. N. Najm, "Efficient block-based parameterized timing analysis covering all potentially critical paths," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 4, pp. 472-484, April 2012. [pdf]

  41. S. Chatterjee, M. Fawaz, and F. N. Najm, "Redundancy-aware power grid electromigration checking under workload uncertainties," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 9, pp. 1509-1522, September 2015. [pdf]

  42. M. Avci and F. N. Najm, "Verification of the power and ground grids under general and hierarchical constraints," IEEE Transactions on VLSI Systems, vol. 24, No. 2, pp. 729-742, February 2016. [pdf]

  43. Z. Moudallal and F. N. Najm, "Generating current budgets to guarantee power grid safety," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1914-1927, November 2016. [pdf]

  44. M. Fawaz and F. N. Najm, "Fast vectorless RLC grid verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 3, pp. 489-502, March 2017. doi:10.1109/TCAD.2016.2589899 (July 12, 2016) [pdf]

  45. S. Chatterjee, V. Sukharev and F. N. Najm, "Power grid electromigration checking using physics-based models," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 37, no. 7, pp. 1317-1330, July 2018. doi:10.1109/TCAD.2017.2666723 (Feb. 9, 2017) [pdf]

  46. Z. Moudallal and F. N. Najm, "Generating current constraints to guarantee RLC power grid safety," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 4, pp. 66:1-66:39, June 2017. doi:10.1145/3054746 (June 2017) [pdf]

  47. V. Sukharev and F. N. Najm, "Electromigration check: where the design and reliability methodologies meet," IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 18, No. 4, pp. 498-507, December 2018. doi:10.1109/TDMR.2018.2874244 (Oct. 5, 2018) [pdf]

  48. Z. Moudallal and F. N. Najm, "Power scheduling with active RC power grids," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 2, pp. 444-457, February 2019. doi:10.1109/TVLSI.2018.2877107 (Nov. 15, 2018) [pdf]

  49. F. N. Najm and V. Sukharev, "Electromigration simulation and design considerations for integrated circuit power grids," Journal of Vacuum Science & Technology B, Vol. 38, No. 6, pp. 063204:1-12, Nov/Dec 2020. doi:10.1116/6.0000476 (Oct. 20, 2020) [pdf]

  50. S. Torosyan, A. Kteyan, V. Sukharev, J.-H. Choy and F. N. Najm, "Novel physics-based tool-prototype for electromigration assessment in commercial-grade power delivery networks," Journal of Vacuum Science & Technology B, Vol. 39, No. 1, pp. 013203:1-6, Jan/Feb 2021. doi:10.1116/6.0000617 (Dec. 21, 2020) [pdf]

  51. F. N. Najm, "Equivalent circuits for electromigration," Microelectronics Reliability, Vol. 123, pp. 114200:1-16, Aug. 2021. doi:10.1016/j.microrel.2021.114200 (June 24, 2021) [pdf]

  52. V. Sukharev, A. Kteyan, F. N. Najm, Y. H. Yi, C. H. Kim, J.-H. Choy, S. Torosyan and Y. Zhu, "Experimental validation of a novel methodology for electromigration assessment in on-chip power grids," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 41, No. 11, pp. 4837-4850, November 2022. doi:10.1109/TCAD.2021.3134886 (Dec. 13, 2021) [pdf]

  53. T. Hou, F. N. Najm, N. Wong and H.-B. Chen, "Novel partitioning-based approach for electromigration assessment with neural networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-14, (accepted April 24, 2025).

Preprints and Magazine Articles:

  1. F. Najm, "Estimating power dissipation in VLSI circuits," IEEE Circuits and Devices Magazine, vol. 10, no. 4, pp. 11-19, July 1994. [ps] [pdf]

  2. F. Najm and J. Abraham, "Accounting for very deep sub-micron effects in silicon models," EE-Times , Jan 09, 2001. [pdf1] [pdf2]

  3. A. Goyal and F. N. Najm, "Efficient RC power grid verification using node elimination," Tech Design Forum, pp. 32-38, June 2011. [pdf]

  4. F. N. Najm, "Model order reduction for lumped RC transmission lines," IEEE TechRxiv , October 17, 2020. 10.36227/techrxiv.13103294.v2 (preprint)

Conference Papers:

  1. I. Hajj and F. Najm, "Test generation for physical faults in MOS VLSI circuits," IEEE 1987 CompEuro Conference: VLSI & Computers, Hamburg, West Germany, pp. 386-389, May 11-15, 1987. [pdf]

  2. R. Burch, F. Najm, P. Yang, and D. Hocevar, "Pattern-independent current estimation for reliability analysis of CMOS circuits," 25th ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 294-299, June 12-15, 1988. [ps] [pdf]

  3. F. Najm, R. Burch, P. Yang, and I. Hajj, "CREST - a current estimator for CMOS circuits," IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 204-207, November 7-10, 1988. [ps] [pdf]

  4. F. Najm, I. Hajj, and P. Yang, "Electromigration median time-to-failure based on a stochastic current waveform," IEEE International Conference on Computer-Design, Cambridge, MA, pp. 447-450, October 2-4, 1989. [ps] [pdf]

  5. F. Najm, I. Hajj, and P. Yang, "Computation of bus current variance for reliability estimation of VLSI circuits," IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 202-205, November 6-9, 1989. [ps] [pdf]

  6. F. Najm and I. Hajj, "Probabilistic simulation of very large scale integrated circuits and systems," 1990 Bilkent International Conference on New Trends in Communications, Control, and Signal Processing, Bilkent University, Ankara, Turkey, July 2-5, 1990.

  7. F. Najm, "Transition density, a stochastic measure of activity in digital circuits," 28th ACM/IEEE Design Automation Conference, San Francisco, CA, pp. 644-649, June 17-21, 1991. [ps] [pdf]

  8. H. Kriplani, F. Najm, and I. Hajj, "Maximum current estimation in CMOS circuits," 29th ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 2-7, June 8-12, 1992. [ps] [pdf]

  9. R. Burch, F. Najm, P. Yang, and T. Trick, "McPOWER: A Monte Carlo approach to power estimation," IEEE/ACM International Conference on Computer-Aided Design, Santa Clara, CA, pp. 90-97, November 8-12, 1992. [ps] [pdf]

  10. H. Kriplani, F. Najm, and I. Hajj, "Resolving signal correlations for estimating maximum currents in CMOS combinational circuits," 30th ACM/IEEE Design Automation Conference, Dallas, TX, pp. 384-388, June 14-18, 1993. [ps] [pdf]

  11. H. Kriplani, F. Najm, and I. Hajj, "Worst case voltage drops in power and ground buses of CMOS VLSI circuits," SRC TECHON'93 Conference, Atlanta, GA, pp. 402-404, September 28-30, 1993. [ps] [pdf]

  12. F. Najm, "Improved Estimation of the Switching Activity for Reliability Prediction in VLSI Circuits," IEEE Custom Integrated Circuits Conference, San Diego, CA, pp. 429-432, May 1-4, 1994. [ps] [pdf]

  13. M. Xakellis and F. Najm, "Statistical Estimation of the Switching Activity in Digital Circuits," 31st ACM/IEEE Design Automation Conference, San Diego, CA, pp. 728-733, 1994. [ps] [pdf]

  14. H. Kriplani, F. Najm, and I. Hajj, "Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits," IEEE International Symposium on Circuits and Systems, vol. 1, pp. 435-438, 1994. [ps] [pdf]

  15. F. N. Najm, "Towards a high-level power estimation capability," IEEE International Symposium on Low Power Design, Dana Point, CA, pp. 87-92, April 23-26, 1995. [ps] [pdf]

  16. V. P. Dabholkar, S. Chakravarty, F. Najm, and J. Patel, "Cyclic stress tests for full scan circuits," IEEE VLSI Test Symposium, Princeton, NJ, pp. 89-94, April 30-May 3, 1995. [ps] [pdf]

  17. R. Panda and F. N. Najm, "Technology decomposition for low-power synthesis," IEEE Custom Integrated Circuits Conference, Santa Clara, CA, pp. 627-630, May 1-4, 1995. [ps] [pdf]

  18. F. N. Najm and M. Y. Zhang, "Extreme delay sensitivity and the worst-case switching activity in VLSI circuits," ACM/IEEE Design Automation Conference, San Francisco, CA, pp. 623-627, June 12-16, 1995. [ps] [pdf]

  19. F. N. Najm, S. Goel, and I. N. Hajj, "Power estimation in sequential circuits," ACM/IEEE Design Automation Conference, San Francisco, CA, pp. 635-640, June 12-16, 1995. [ps] [pdf]

  20. F. N. Najm, "Feedback, correlation, and delay concerns in the power estimation of VLSI circuits," ACM/IEEE Design Automation Conference, San Francisco, CA, pp. 612-617, June 12-16, 1995. (Invited Paper) [ps] [pdf]

  21. F. N. Najm, "Power Estimation Techniques for Integrated Circuits," IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 492-499, June 12-16, 1995. (Invited Tutorial Paper) [ps] [pdf]

  22. M. Nemani and F. N. Najm, "High-Level Power Estimation and the Area Complexity of Boolean Functions," IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 329-334, August 12-14, 1996. [ps] [pdf]

  23. Luis E. Amaya, Philip T. Krein, and Farid N. Najm, "A Synthesis Environment for Power Electronics," 5th IEEE Workshop on Computers in Power Electronics, Portland, OR, August 11-14, 1996. [ps] [pdf]

  24. V. Saxena, F. N. Najm, and I. N. Hajj, "Monte-Carlo approach for power estimation in sequential circuits," European Design & Test Conference, Paris, France, March 17-20, 1997. [ps] [pdf]

  25. J. P. Halter and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," IEEE Custom Integrated Circuits Conference, Santa Clara, CA, pp. 475-478, May 5-8, 1997. [ps] [pdf]

  26. M. Nemani and F. N. Najm, "High-level area prediction for power estimation," IEEE Custom Integrated Circuits Conference, Santa Clara, CA, pp. 475-478, May 5-8, 1997. [ps] [pdf]

  27. S. Gupta and F. N. Najm, "Power macromodeling for high level power estimation," 34th Design Automation Conference, pp. 365-370, Anaheim, CA, June 9-13, 1997. [ps] [pdf]

  28. R. Panda and F. N. Najm, "Technology-dependent transformations for low-power synthesis," 34th Design Automation Conference, pp. 650-655, Anaheim, CA, June 9-13, 1997. [ps] [pdf]

  29. M. Nemani and F. N. Najm, "High-level area and power estimation for VLSI circuits," IEEE/ACM International Conference on Computer-Aided Design, pp. 114-119, Nov. 1997. [ps] [pdf]

  30. J. N. Kozhaya and F. N. Najm, "Accurate power estimation for large sequential circuits," IEEE/ACM International Conference on Computer-Aided Design, pp. 488-493, Nov. 1997. [ps] [pdf]

  31. M. Nemani and F. N. Najm, "Delay estimation for VLSI circuits from a high-level view," 35th Design Automation Conference, pp. 591-594, San Francisco, CA, June 15-19, 1998. [ps] [pdf]

  32. S. Gupta and F. N. Najm, "Analytical model for high level power modeling of combinational and sequential circuits," IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como, Italy, pp. 164-172, March 4-5, 1999. [ps] [pdf]

  33. S. Gupta and F. N. Najm, "Energy-per-cycle estimation at RTL," IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 121-126, Aug. 16-17, 1999. [ps] [pdf]

  34. S. Gupta and F. N. Najm, "Power macro-models for DSP blocks with application to high-level synthesis," IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 103-105, Aug. 16-17, 1999. [ps] [pdf]

  35. S. Ramprasad, I. N. Hajj, and F. N. Najm, "An optimization technique for dual-output domino logic," IEEE International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 121-126, Aug. 16-17, 1999. [ps] [pdf]

  36. G. Yoh and F. N. Najm, "A statistical model for electromigration failures," IEEE 2000 1st International Symposium on Quality Electronic Design, San Jose, CA, pp. 45-50, March 20-22, 2000. [ps] [pdf]

  37. S. Bodapati and F. N. Najm, "Pre-layout estimation of individual wire lengths," ACM International Workshop on System-Level Interconnect Prediction, San Diego, CA, pp. 93-98, April 8-9, 2000. [ps] [pdf]

  38. K. M. Buyuksahin and F. N. Najm, "High-level power estimation with interconnect effects," IEEE International Symposium on Low Power Electronics and Design, Italy, pp. 197-202, July 26-27, 2000. [ps] [pdf]

  39. S. Bodapati and F. N. Najm, "Frequency-domain supply current macro-model," IEEE International Symposium on Low Power Electronics and Design, pp. 295-298, Aug. 2001. [ps] [pdf]

  40. J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "I/O buffer placement methodology for ASICs," 8th IEEE International Conference on Electronics, Circuits and Systems, Malta, pp. 245-248, Sept. 2001. [ps] [pdf]

  41. M. Shahriari and F. N. Najm, "A gate-level timing model for SOI circuits," 8th IEEE International Conference on Electronics, Circuits and Systems, Malta, pp. 795-798, Sept. 2001. [ps] [pdf]

  42. J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "Multigrid-like technique for power grid analysis," IEEE/ACM International Conference on Computer-Aided Design, pp. 480-487, Nov. 2001. [ps] [pdf]

  43. N. Azizi, A. Moshovos, and F. N. Najm, "Low-leakage asymmetric-cell SRAM," IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 48-51, August 12-14, 2002. [ps] [pdf]

  44. K. M. Buyuksahin and F. N. Najm, "High-level area estimation," IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, pp. 271-274, August 12-14, 2002. [ps] [pdf]

  45. J. H. Anderson and F. N. Najm, "Power-aware technology mapping for LUT-based FPGAs," IEEE International Conference on Field-Programmable Technology, Hong Kong, pp. 211-218, December 16-18, 2002. [ps] [pdf]

  46. J. H. Anderson and F. N. Najm, "Switching activity analysis and pre-layout activity prediction for FPGAs," ACM/IEEE International Workshop on System-Level Interconnect Prediction, Monterey, CA, pp. 15-21, April 5-6, 2003. [ps] [pdf]

  47. R. S. Guindi and F. N. Najm, "Design techniques for gate-leakage reduction in CMOS circuits," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, pp. 61-65, March 24-26, 2003. [ps] [pdf]

  48. I. A. Ferzli and F. N. Najm, "Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations," ACM/IEEE 40th Design Automation Conference (DAC-03), Anaheim, CA, pp. 856-859, June 2-6, 2003. [ps] [pdf]

  49. D. Kouroussis and F. N. Najm, "A static pattern-independent technique for power grid voltage integrity verification," ACM/IEEE 40th Design Automation Conference (DAC-03), Anaheim, CA, pp. 99-104, June 2-6, 2003. [ps] [pdf]

  50. R. S. Guindi, R. C. Kordasiewicz, and F. N. Najm, "Optimization technique for FB/TB assignment in PD-SOI digital CMOS circuits," The First Annual Northeast Workshop on Circuits and Systems (NEWCAS), Montreal, Quebec, Canada, pp. 157-160, June 17-20, 2003. [ps] [pdf]

  51. R. Ahmadi and F. N. Najm, "Timing analysis in presence of power supply and ground voltage variations," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, pp. 176-183, November 9-13, 2003. [ps] [pdf]

  52. I. A. Ferzli and F. N. Najm, "Statistical verification of power grids considering process-induced leakage current variations," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, pp. 770-777, November 9-13, 2003. [ps] [pdf]

  53. J. H. Anderson and F. N. Najm, "Interconnect capacitance estimation for FPGAs," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 713-718, January 27-30, 2004. [pdf]

  54. J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, pp. 33-41, February 22-24, 2004. [pdf]

  55. N. Azizi and F. N. Najm, "An asymmetric SRAM cell to lower gate leakage," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, pp. 534-539, March 22-24, 2004. [pdf]

  56. I. A. Ferzli and F. N. Najm, "Statistical estimation of circuit timing vulnerability due to leakage-induced power grid voltage drop," IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Austin, TX, pp. 17-24, May 17-20, 2004. (Invited Paper) [pdf]

  57. F. N. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," ACM/IEEE 41st Design Automation Conference (DAC), San Diego, CA, pp. 460-465, June 7-11, 2004. [pdf]

  58. B. Wu, J. Zhu, and F. N. Najm, "An analytical approach for dynamic range estimation," ACM/IEEE 41st Design Automation Conference (DAC), San Diego, CA, pp. 472-477, June 7-11, 2004. [pdf]

  59. D. Kouroussis, R. Ahmadi, and F. N. Najm, "Worst-case circuit delay taking into account power supply variations," ACM/IEEE 41st Design Automation Conference (DAC), San Diego, CA, pp. 652-657, June 7-11, 2004. [pdf]

  60. D. Kouroussis, R. Ahmadi, and F. N. Najm, "A worst-case circuit delay verification technique considering power grid voltage variations," The 2nd Annual Northeast Workshop on Circuits and Systems (NEWCAS-04), Montreal, Quebec, pp. 157-160, June 20-23, 2004. [pdf]

  61. J. H. Anderson and F. N. Najm, "A novel low-power FPGA routing switch," IEEE Custom Integrated Circuits Conference (CICC), Orlando, FL, pp. 719-722, October 3-6, 2004. [pdf]

  62. J. H. Anderson and F. N. Najm, "Low-power programmable routing circuitry for FPGAs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, pp. 602-609, November 7-11, 2004. [pdf]

  63. B. Wu, J. Zhu, and F. N. Najm, "Dynamic range estimation for nonlinear systems," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, pp. 660-667, November 7-11, 2004. [pdf]

  64. N. Azizi, M. M. Khellah, V. De, and F. N. Najm, "Variations-aware low-power design with voltage scaling," ACM/IEEE 42nd Design Automation Conference (DAC-05), Anaheim, CA, pp. 529-534, June 13-17, 2005. [pdf]

  65. F. N. Najm, "On the need for statistical timing analysis," ACM/IEEE 42nd Design Automation Conference (DAC-05), Anaheim, CA, pp. 764-765, June 13-17, 2005. [pdf]

  66. B. Wu, J. Zhu, and F. N. Najm, "A non-parametric approach for dynamic range estimation of nonlinear systems," ACM/IEEE 42nd Design Automation Conference (DAC-05), Anaheim, CA, pp. 841-844, June 13-17, 2005. [pdf]

  67. N. Azizi and F. N. Najm, "Compensation for within-die variations in dynamic logic by using body-bias," Northeast Workshop on Circuits and Systems (NEWCAS-05), Quebec City, QC, Canada, pp. 167-170, June 19-22, 2005. [pdf]

  68. G. Nabaa and F. N. Najm, "Minimization of delay sensitivity to process induced voltage threshold variations," Northeast Workshop on Circuits and Systems (NEWCAS-05), Quebec City, QC, Canada, pp. 171-174, June 19-22, 2005. [pdf]

  69. K. R. Heloue and F. N. Najm, "Effect of statistical clock skew variations on chip timing yield," Northeast Workshop on Circuits and Systems (NEWCAS-05), Quebec City, QC, Canada, pp. 211-214, June 19-22, 2005. [pdf]

  70. M. Nizam, F. N. Najm, and A. Devgan, "Power grid voltage integrity verification," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-05), San Diego, CA, pp. 239-244, August 8-10, 2005. [pdf]

  71. N. Azizi and F. N. Najm, "Look-up table leakage reductions for FPGAs," IEEE Custom Integrated Circuits Conference (CICC-05), San Jose, CA, pp. 187-190, September 18-21, 2005. [pdf]

  72. D. Kouroussis, I. A. Ferzli, and F. N. Najm, "Incremental partitioning-based vectorless power grid verification," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), San Jose, CA, pp. 358-364, November 6-10, 2005. [pdf]

  73. K. R. Heloue and F. N. Najm, "Statistical timing analysis with two-sided constraints," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), San Jose, CA, pp. 829-836, November 6-10, 2005. [pdf]

  74. G. Nabaa, N. Azizi, and F. N. Najm, "An adaptive FPGA architecture with process variation compensation and reduced leakage," ACM/IEEE 43rd Design Automation Conference (DAC-06), San Francisco, CA, pp. 624-629, July 24-28, 2006. [pdf]

  75. N. Azizi, and F. N. Najm, "A family of cells to reduce the soft-error-rate in ternary-CAM," ACM/IEEE 43rd Design Automation Conference (DAC-06), San Francisco, CA, pp. 779-784, July 24-28, 2006. [pdf]

  76. K. Pagiamtzis, N. Azizi, and F. N. Najm, "A soft-error tolerant content-addressable memory (CAM) using an error-correcting-match scheme," IEEE Custom Integrated Circuits Conference (CICC-06), San Jose, CA, pp. 301-304, September 10-13, 2006. [pdf]

  77. N. H. Abdul Ghani and F. N. Najm, "Handling inductance in early power grid verification," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-06), San Jose, CA, pp. 127-134, November 5-9, 2006. [pdf]

  78. S. Onaissi and F. N. Najm, "A Linear-Time Approach for Static Timing Analysis Covering All Process Corners," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-06), San Jose, CA, pp. 217-224, November 5-9, 2006. [pdf]

  79. H. Mangassarian, A. Veneris, S. Safarpour, F. N. Najm, and M. S. Abadir, "Maximum circuit activity estimation using pseudo-Boolean satisfiability," Design, Automation and Test in Europe (DATE-07), Nice, France, pp. 1538-1543, April 16-20, 2007. [pdf]

  80. N. Azizi and F. N. Najm, "Using keeper control and body bias for fine grained threshold voltage compensation in dynamic logic," 20th Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, pp. 1639-1644, April 22-26, 2007. [pdf]

  81. K. R. Heloue and F. N. Najm, "Early statistical timing analysis with unknown within-die correlations," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-07), Austin, TX, pp. 13-18, February 26-27, 2007. [pdf]

  82. K. R. Heloue and F. N. Najm, "Early analysis of timing margins and yield," 20th Canadian Conference on Electrical and Computer Engineering, Vancouver, BC, pp. 1114-1120, April 22-26, 2007. [pdf]

  83. K. R. Heloue, N. Azizi, and F. N. Najm, "Modeling and estimation of full-chip leakage current considering within-die correlation," ACM/IEEE 44th Design Automation Conference (DAC-07), San Diego, CA, pp. 93-98, June 4-8, 2007. [pdf]

  84. I. A. Ferzli, F. N. Najm, and L. Kruse, "Early power grid verification under circuit current uncertainties," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED-07), Portland, OR, pp. 116-121, August 27-29, 2007. [pdf]

  85. I. A. Ferzli, F. N. Najm, and L. Kruse, "A geometric approach for early power grid verification using current constraints," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-07) San Jose, CA, pp. 40-47, November 5-8, 2007. [pdf]

  86. K. R. Heloue and F. N. Najm, "Parameterized timing analysis with general delay models and arbitrary variation sources," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-08), Monterey, CA, pp. 14-19, February 25-26, 2008. [pdf]

  87. K. R. Heloue and F. N. Najm, "Parameterized timing analysis with general delay models and arbitrary variation sources," ACM/IEEE 45th Design Automation Conference (DAC-08), Anaheim, CA, pp. 403-408, June 8-13, 2008. [pdf]

  88. I. A. Ferzli, E. Chiprout, and F. N. Najm, "Verification and co-design of the package and die power delivery system using wavelets," IEEE Conference on Electrical Performance of Electronic Packaging (EPEP), San Jose, CA, pp. 7-10, October 27-29, 2008. [pdf]

  89. K. R. Heloue, S. Onaissi, and F. N. Najm, "Efficient block-based parameterized timing analysis covering all potentially critical paths," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-08), San Jose, CA, pp. 173-180, November 10-13, 2008. [pdf]

  90. K. R. Heloue, C. V. Kashyap, and F. N. Najm, "Quantifying robustness metrics in parameterized static timing analysis,'' ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-09), Austin, TX, pp. 49-54, February 23-24, 2009. [pdf]

  91. N. H. Abdul Ghani and F. N. Najm, "Fast vectorless power grid verification using an approximate inverse technique," ACM/IEEE 46th Design Automation Conference (DAC-09), San Francisco, CA, pp. 184-189, July 26-31, 2009. [pdf]

  92. S. Onaissi, K. R. Heloue, and F. N. Najm, "Clock skew optimization via wiresizing for timing sign-off covering all process corners," ACM/IEEE 46th Design Automation Conference (DAC-09), San Francisco, CA, pp. 196-201, July 26-31, 2009. [pdf]

  93. K. R. Heloue, C. V. Kashyap, and F. N. Najm, "Quantifying robustness metrics in parameterized static timing analysis," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-09), San Jose, CA, pp. 209-216, November 2-5, 2009. [pdf]

  94. S. Onaissi, K. R. Heloue, and F. N. Najm, "PSTA-based branch and bound approach to the Silicon speedpath isolation problem," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-09), San Jose, CA, pp. 217-224, November 2-5, 2009. [pdf]

  95. S. Safarpour, A. Veneris, and F. N. Najm, "Managing verification error traces with bounded model debugging," The 15th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp. 601-606, Jan. 18-21, 2010. [pdf]

  96. M. Aydonat and F. N. Najm, "Power grid correction using sensitivity analysis," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-10), San Jose, CA, pp. 808-815, November 7-11, 2010. [pdf]

  97. M. Avci and F. N. Najm, "Early P/G grid voltage integrity verification," ACM/IEEE International Conference on Computer-Aided Design (ICCAD-10), San Jose, CA, pp. 816-823, November 7-11, 2010. [pdf]

  98. A. Goyal and F. N. Najm, "Efficient RC power grid verification using node elimination," Design, Automation and Test in Europe (DATE-11), Grenoble, France, pp. 257-260, March 14-18, 2011. [pdf]

  99. N. H. Abdul Ghani and F. N. Najm, "Power grid verification using node and branch dominance," ACM/IEEE 47th Design Automation Conference (DAC-2011), San Diego, CA, pp. 682-687, June 5-9, 2011. [pdf]

  100. P. Al Haddad and F. N. Najm, "Power grid correction using sensitivity analysis under an RC model," ACM/IEEE 47th Design Automation Conference (DAC-2011), San Diego, CA, pp. 688-693, June 5-9, 2011. [pdf]

  101. S. Onaissi, F. Taraporevala, J. Liu, and F. N. Najm, "A fast approach for static timing analysis covering all PVT corners," ACM/IEEE 47th Design Automation Conference (DAC-2011), San Diego, CA, pp. 777-782, June 5-9, 2011. [pdf]

  102. Abhishek and F. N. Najm, "Incremental power grid verification," ACM/IEEE 48th Design Automation Conference (DAC-2012), San Francisco, CA, pp. 151-156, June 3-7, 2012. [pdf]

  103. F. N. Najm, "Overview of vectorless/early power grid verification," ACM/IEEE International Conference on Computer-Aided Design, San Jose, CA, pp. 670-677, November 5-8, 2012. (Invited Paper) [pdf]

  104. S. Chatterjee, M. Fawaz, and F. N. Najm, "Redundancy-aware electromigration checking for mesh power grids," ACM/IEEE International Conference on Computer-Aided Design, San Jose, CA, pp. 540-547, November 18-21, 2013. [pdf]

  105. M. Fawaz, S. Chatterjee, and F. N. Najm, "A vectorless framework for power grid electromigration checking," ACM/IEEE International Conference on Computer-Aided Design, San Jose, CA, pp. 553-560, November 18-21, 2013. [pdf]

  106. Z. Moudallal and F. N. Najm, "Generating circuit current constraints to guarantee power grid safety," 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, pp. 358-365, January 19-22, 2015. [pdf]

  107. M. Fawaz and F. N. Najm, "Accurate verification of RC power grids," Design, Automation and Test in Europe (DATE-16), Dresden, Germany, pp. 814-817, March 14-18, 2016. [pdf]

  108. M. Fawaz and F. N. Najm, "Fast simulation-based verification of RC power grids," IEEE Canadian Conference on Electrical and Computer Engineering (CCECE-16), Vancouver, Canada, pp. 1182-1187, May 15-18, 2016. [pdf]

  109. Z. Moudallal and F. N. Najm, "Generating voltage drop aware current budgets for RC power grids," IEEE International Symposium on Circuits and Systems (ISCAS-16), Montreal, Canada, pp. 2583-2586, May 22-25, 2016. [pdf]

  110. A.-A. Yassine and F. N. Najm, "A fast layer elimination approach for power grid reduction," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-16), Austin, TX, pp. 8B.4, November 7-10, 2016. [pdf]

  111. S. Chatterjee, V. Sukharev and F. N. Najm, "Fast physics-based electromigration checking for on-die power grids," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-16), Austin, TX, pp. 9A.1, November 7-10, 2016. (Best Paper Award) [pdf]

  112. V. Sukharev, A. Kteyan, J.-H. Choy, S. Chatterjee and F. N. Najm, "Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids with analytical and numerical analysis," IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, pp. 6B.5, April 2-6, 2017. (Invited Paper) [pdf]

  113. M. Fawaz and F. N. Najm, "Parallel simulation-based verification of RC power grids," IEEE Computer Society Annual Symposium on VLSI (ISVLSI-17), Bochum, Germany, pp. 445-452, July 3-5, 2017. [pdf]

  114. J.-H. Choy, V. Sukharev, S. Chatterjee, F. N. Najm, A. Kteyan and S. Moreau, "Finite-difference methodology for full chip electromigration analysis applied to a 3D IC test structure: Simulation vs. experiment," IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD-17), Kamakura, Japan, pp. 41-44, September 7-9, 2017. [pdf]

  115. Z. Moudallal and F. N. Najm, "Power scheduling with active power grids," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-17), Irvine, CA, pp. 466-473, November 13-16, 2017. [pdf]

  116. M. Fawaz and F. N. Najm, "Power grid verification under transient constraints," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-17), Irvine, CA, pp. 593-600, November 13-16, 2017. [pdf]

  117. S. Chatterjee, V. Sukharev and F. N. Najm, "Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-17), Irvine, CA, pp. 659-666, November 13-16, 2017. [pdf]

  118. F. N. Najm and V. Sukharev, "Efficient simulation of electromigration damage in large chip power grids using accurate physical models," IEEE International Reliability Physics Symposium (IRPS-19), Monterey, CA, pp. 2A.1-1 - 2A.1-10, March 31 - April 3, 2019. (Invited Paper) [pdf]

  119. Z. Moudallal, V. Sukharev and F. N. Najm, "Power grid fixing for electromigration-induced voltage failures," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-19), Westminster, CO, pp. 1-8, November 4-7, 2019. (Best Paper Award) [pdf]

  120. A. Issa, V. Sukharev and F. N. Najm, "Electromigration checking using a stochastic effective current model," IEEE/ACM International Conference on Computer-Aided Design (ICCAD-20), pp. 1-8, November 2-5, 2020. (Best Paper Award) [pdf]

  121. A. Kteyan, V. Sukharev, A. Volkov, J-H. Choy, F. N. Najm, Y. H. Yi, C. H. Kim and S. Moreau, "Electromigration assessment in power grids with account of redundancy and non-uniform temperature distribution," ACM International Symposium on Physical Design (ISPD-23), (virtual), pp. 124-132, March 26-29, 2023. [pdf]

  122. B. Shahriari and F. N. Najm, "Fast electromigration simulation for chip power grids," IEEE International Symposium on Quality Electronic Design (ISQED-23), San Francisco, CA, pp. 502-509, April 5-7, 2023. [pdf]

  123. C. Feghali and F. N. Najm, "Fast current constraints generation for chip safety," IEEE International Symposium on Quality Electronic Design (ISQED-24), San Francisco, CA, pp. 373-380, April 3-5, 2024. [pdf]

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